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Sub-electron noise charge-coupled
devices
Charles E. Chandler, Richard A. Bredthauer, James R.
Janesick, James A. Westphal
Charles E. Chandler, Richard A. Bredthauer, James R. Janesick, James A.
Westphal, "Sub-electron noise charge-coupled devices," Proc. SPIE 1242,
Charge-Coupled Devices and Solid State Optical Sensors, (1 July 1990); doi:
10.1117/12.19457
Event: Electronic Imaging: Advanced Devices and Systems, 1990, Santa
Clara, CA, United States
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Sub-electron noise charge coupled devices
Charles E. Chandler, Richard A. Bredthauer
Ford Aerospace Corporation
Ford Road, Newport Beach, California 92658
James R. Janesick
Jet Propulsion Laboratory
4800 Oak Grove Drive, Pasadena, California 91109
James A. Westphal
California Institute of Technology
Pasadena, California 91125
James E. Gunn
Princeton University
Princeton, New Jersey, 08544
ABSTRACT
A charge coupled device designed for celestial spectroscopy has achieved readout noise as low as 0.6 electrons
rms. A non-destructive output circuit was operated in a special manner to read a single pixel multiple times. Off-
chip electronics averaged the multiple values, reducing the random noise by the square root of the number of
readouts. Charge capacity was measured to be 500,000 electrons. The device format is 1600 pixels horizontal
by 64 pixels vertical. Pixel size is 28 microns square. Two output circuits are located at opposite ends of the 1600
bit CCD register. The device was thinned and operated backside illuminated at -1 10 degrees C. Output circuit
design, layout, and operation are described. Presented data includes the photon transfer curve, noise histograms,
and bar-target images down to 3 electrons signal. The test electronics are described, and future improvements
are discussed.
.
1.
CCD READOUT CIRCUIT NOISE
The state of the art silicon substrate quality and wafer fabrication can combine to produce CCD registers with
nearly perfect charge transfer efficiency (CTE)1. By cooling such a CCD to a sufficiently low temperature to
reduce the dark current, single photo-electrons can be transferred to the CCD output circuit. Readout noise then
limits the signal to noise ratio for very low background CCD applications. In this paper we explain the problems
and a solution for obtaining sub-electron readout noise. The two most common forms of CCD output circuits,
floating diffusion and floating gate, are considered for sub-electron noise operation. Other output circuits have
been proposed2, but require additional wafer processing complexity, and so are not likely to be adopted by
manufacturers of large format CCD's.
1.1 Floating diffusion output circuit
Electrons that are clocked out of the CCD onto the output node cause a voltage change according to the equation
Vo =
qN/C
where q is the electron charge, N is the number of electrons, and C is the output node capacitance.
In general, minimizing C increases the output sensitivity and reduces the noise, as we will show later. The
minimum value of C is limited by the layout rules which are set by mask alignment tolerances and lithography
limitations.
238
/ SPIE Vol. 1242 Charge-Coupled Devices and Solid State Optical Sensors (1990)
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1.2 Floating gate output circuit
Another type of output circuit is the floating gate (FG) output circuits, which also exists in "distributed" form
using multiple floating gates. The resettable PG output has a slightly higher output node capacitance than the
PD output due to the additional capacitance of the floating gate over the CCD channel. The floating gate cannot
be made arbitrarily small, because it must be large enough to hold the desired maximum charge. For the PD
output, the output node capacitance can be made as small as the layout rules allow. For the same output
MOSFET, therefore, the higher node capacitance of the FG output will result in a slightly higher noise level than
for the FD output. The FG output has the option of being operated with a reset pulse every line of pixels instead
of every pixel. For lowest noise, however, the correlated double sampler (CDS) must still sample the output
before and after each pixel output, in order to suppress the MOSFET 1/f noise a much as possible.
1.3 Noise reduction limit
For either FD or FG outputs, if the output MOSFET gate area is decreased in order to increase the CCD output
sensitivity, the 1/f noise component increases inversely proportional to the MOSFET gate area4. At high clock
frequencies the 1/f knee is typically well below the clock rate. Since 1/f noise is not a problem at high
frequencies, much progress has been made in reducing the readout noise of outputs operating at multi-megahertz
clock rates by increasing the sensitivity. These same output circuits suffer greatly from 1/f noise if operated at
kilohertz data rates. The 1/f noise problem is illustrated in figure 1. The input noise of a MOSFET with a 20KHz
-1— ÷
-1—
-4-
\
CDS
curves shown 5X for detail, 50K pixels/second:
\
#1:
Dual RC Integrator, gate=7u5, pitch=8uS, RC=l4uS
\
#2:
Clamp & Sample, clamp=l2uS, sample=5uS, RC=2.5uS
\
Pet
noise
1/f "knee" =
20KHz
#1
Frequency
Figure 1. MOSFET noise and CDS response
1/f knee is plotted along with the resulting noise spectrum after CDS. The two curves show the clamp-and-
sample and the reset integrator CDS response normalized to an equal signal level for a pixel rate of 50KHz.
Appendix A explains how the curves were calculated. With either type of CDS, if the operating frequency is
reduced from 50KHz, the CDS response peak will increasingly overlap with the 1/f noise, preventing a significant
50
40
30
Noise
(nV/Hz)
20
10
#2
100
A
0 +
4-
÷
.4..
1K
10K
lOOK
1M
1OM
SPIE Vol. 1242 Charge-Coupled Devices and Solid State Optical Sensors (1990) / 239
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decrease in the readout noise. If MOSFET's could be made (compatible with CCD wafer processing) without 1/f
noise, then sub-electron readout noise would be rather easy to obtain. Since without 1/f noise the readout noise
would vary inversely proportional to the square root of the clock rate, an output achieving 5 electrons noise at
50KHz could reach 1 electron noise at (5OKHz)/(5x5) or 2KHz. With a special output circuit and the appropriate
signal processing techniques, the ever-present 1/f noise barrier can be broken, as will now be described.
2. AVERAGING FLOATING GATE OUTPUT CIRCUIT
The approach taken in this work was to surround a FG output circuit with CCD gates to enable repetitive, non-
destructive readout of the signal charge. Thus, the output circuit timing can be adjusted such that the CDS
response is above the MOSFET 1/f noise regime, and multiple readouts of the same signal can be averaged off-
chip to reduce the noise. For a device cooled below -100 degrees C, the slowest tolerable frame rate will
determine the maximum number of averages, not a theoretical limit. For applications that cannot be cooled
sufficiently, dark current generation will be the limit. A dark signal of only one electron every four pixels is 0.25e
average, or 0.5e rms nise.
____________
(÷7V)
RESET DRAIN
Figure 2. Output circuit operation
240 / SPIE Vol. 1242 Charge-Coupled Devices and Solid State Optical Sensors (1990)
RESET GATE ____________
OUTPUT GATE
SUMvIING GATE
CCD CCD CCD
1
2 3
ww_
OUTPUT DRAIN
C+20V)
OUTPUT SOURCE
C RL=20K)
DUMP GATE
_______ DUMP
DRAIN
(+20V)
t=o
t=1 t=2
\I/ \I/
CHARGE
Clock Low
Clock High
TIMING FOR n=3:
CCD 3
SI.MA
INC GATE
OUTPUT GATE
RESET GATE
DUMP GATE
OUTPUT
SOURCE
+1 2V
______I
L_._J
LJ
1
-2V
+gv
____________________ ___________________
Dv
Dv
______ _________ _________ _________
-6V
+9V
-2V
RESET
SIGNAL
1st
2nd 3rd
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2.1 Circuit operation
The averaging FG output circuit is shown schematically in figure 2, along with the clock timing and clock
voltages. The charge sensitive node is a floating gate over the CCD channel, connected to the gate of a MOSFET
source follower. Another MOSFET is connected as a switch to the floating gate in order to reset it to the reset
drain (RD) voltage. On the input side of the floating gate is the CCD output gate COG). Between the OG and
the CCD phase clocks is the summing well gate (SW). In operation, charge is clocked out of CCD phase 3 into
the summing gate, while the reset MOSFET sets the floating gate to the RD voltage (t=O). The off-chip CDS then
captures the reset level. Then SW is clocked low, forcing the charge over OG and under the floating gate (t=1).
Because the gate is floating at this time (reset gate off), the voltage on the gate decreases in proportion to the
number of electrons in the charge packet. The CDS captures the signal level and subtracts the reset level. During
the next reset gate (RG) pulse, OG is clocked high, transferring the charge back into SW (t=2). After the desired
number of readouts of one pixel, the dump gate (DG) is pulsed and the charge is discarded into the dump drain
(DD) at t=3. The floating gate is reset every readout to precisely control the DC level of the gate and add
immunity to parasitic clock coupling.
2.2 Design and layout considerations
Figure 3 shows the actual mask layout of the arrays bottom-left output circuit, with charge traveling from right
to left in the CCD channel. In order to minimize the floating gate node capacitance, the CCD channel width is
reduced from 6(m first to 3Om and then to l5jim. The output MOSFET has a channel width of 100pm and
a gate length of 9jim. Two levels of polysiicon electrodes are required with a total of only six mask layers for
the circuit (the sixth layer defines the bonding pads and is not required in the area shown). Compared to a FD
output, two leads (dump gate and dump drain) have been added. Usually the dump drain can be connected to
the output drain.
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RESET
GATE
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Figure 3. Output circuit mask layout
Design equations that could accurately predict the readout noise level would depend heavily on the details of
the MOSFET white and 1/f noise behavior. Since this in turn varies due to wafer
processing parameters, such
as the surface state density, these equations are only approximations based on empirical calibrations. As a design
aid, though, even a simple equation is valuable. Consider the readout noise NR (electrons) expressed as the total
SPIE
Vol. 1242 Charge-Coupled Devices and Solid State Optical Sensors (1990) / 241
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OUTPUT
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