LBNL-49992: Draft for IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 1, 225-338, JANUARY 2003 101
Fully-Depleted, Back-Illuminated Charge-Coupled
Devices Fabricated on High-Resistivity Silicon
Stephen E. Holland, Donald E. Groom, Nick P. Palaio, Richard J. Stover, Mingzhi Wei
Abstract — Charge-coupled devices (CCD’s) have been fab-
ricated on high-resistivity, n-type silicon. The resistivity,
on the order of 10,000 Ω-cm, allows for depletion depths of
several hundred microns. Fully-depleted, back-illuminated
operation is achieved by the application of a bias voltage to
a ohmic contact on the wafer back side consisting of a thin
in-situ doped polycrystalline silicon layer capped by indium
tin oxide and silicon dioxide. This thin contact allows for
good short wavelength response, while the relatively large
depleted thickness results in good near-infrared response.
Keywords— Charge-coupled device, back illuminated, fully
depleted, high-resistivity silicon.
I. Introduction
T
HE large focal planes at astronomical telescopes re-
quire high quantum efficiency (QE), large format
charge-coupled device (CCD) detectors. In order to achieve
high QE, the standard scientific CCD is thinned and back
illuminated [1]. Thinning is required because the rel-
atively low resistivity silicon used to fabricate scientific
CCD’s limits the depth of the depletion region. In order
to minimize field-free regions with resulting degradation
in spatial resolution, the typical scientific CCD is thinned
to about 20 µm. This process degrades red and near-
infrared response due to the rapid increase in absorption
length in silicon at long wavelengths. In addition, fring-
ing patterns due to multiply-reflected light are observed in
uniformly-illuminated images taken at near-infrared wave-
lengths where the absorption length exceeds the CCD
thickness. The CCD described in this work achieves high
quantum efficiency in the red and near-infrared by virtue
of a thick depleted region made possible by the use of high-
resistivity silicon substrates.
Extended red response is extremely important to the
Supernovae Cosmology Project at Lawrence Berkeley Na-
tional Laboratory (LBNL) due to the use of distant, high
redshift supernovae for the determination of cosmological
parameters [2]. Detection and follow-up spectroscopy of
high redshift objects would greatly benefit from CCD’s
with improved near-infrared response.
We have reported results on a small prototype CCD with
high QE extended to 1000 nm [3], [4]. In this work the
physical operating principles and technology of this CCD
are described along with results on large-format sensors.
S. Holland is with the Lawrence Berkeley National Laboratory,
Berkeley, California, USA. E-mail: seholland@lbl.gov .
D. Groom and N. Palaio are with the Lawrence Berkeley National
Laboratory, Berkeley, California, USA.
R. Stover and M. Wei are with the University of California Obser-
vatories, Santa Cruz, CA.
Buried
p channel
3-phase
CCD structure
lsilicn
ate electrdes
n
Ω-c
ransparent
rear ind
x
y
Bias
ltae
ht-
sensitie
lue
-3µ
Fig. 1. Cross-sectional diagram of the CCD described in this work.
The actual implementation of the substrate bias voltage connection
is described in Section III.
I I. Background
Scientific CCD’s are typically used in applications requir-
ing low level light detection. Hence dark current, noise and
quantum efficiency are of primary importance. For astron-
omy applications the CCD’s are often cooled to −120
◦
C
to −150
◦
C to minimize dark current. In addition read-
out rates are relatively slow, typically 20–50 kpixels/sec, to
minimize read noise [1]. The signal to noise ratio is further
increased by the use of back illumination with correspond-
ingly high quantum efficiency. Large format sensors are
commonly used, and high charge transfer efficiency (CTE)
is required.
Figure 1 shows a cross-section of the CCD considered in
this work. A conventional three-phase, triple polysilicon
gate CCD [5] with buried channel is fabricated on a high-
resistivity n-type substrate. A substrate bias is applied to
fully deplete the substrate, which is typically 200–300 µm
thick. The biasing details are described in Section III. The
CCD’s described in this work are fabricated on 10,000–
12,000 Ω-cm material, corresponding to a donor density
N
D
of approximately 3.6–4.3 × 10
11
cm
−3
. This high resis-
tivity starting material allows for fully depleted operation
at reasonable voltages.
The CCD described here is p-channel. The choice of p-
channel over the more conventional n-channel was due to
our previous experience with fabrication of charged-particle
p-i-n detectors, where we found it more straightforward
to produce low dark current devices via backside getter-
ing techniques on n-type silicon [6]. The degraded read-
out speed resulting from lower hole mobility in a p-channel
CCD is not a concern for the astronomy application due
LBNL-49992: Draft for IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 1, 225-338, JANUARY 2003 102
200 400 600 800 1000300 500 700 900 1100
Wavelength (nm)
10
–
3
10
–
2
10
–
1
10
0
10
1
10
2
10
3
10
4
Absorption length (µm)
77 K
173 K
300 K
Fig. 2. Absorption length versus wavelength for silicon. Data and
calculations (dashed lines) are taken from Reference [18]. Additional
room temperature data (solid line) is taken from Reference [1].
to the relatively low readout rates. P-channel CCD’s are
presently under study for space applications due to the ex-
pected improvement in resistance to damage produced by
high-energy protons in the space environment when com-
pared to n-channel CCD’s [7], [8], [9].
Previous n-channel “deep-depletion CCD’s” [10], [11],
[12], [13], [14] have 40–80 µm thick depletion regions, due to
the use of more highly doped starting silicon and the lack of
a substrate bias voltage. Early work on CCD’s fabricated
on high-resistivity n-type silicon was reported, although
problems with high dark current were noted [15], [16]. The
same group later described fully-depleted, deep-depletion
n-channel CCD’s with implanted backside layers [17]. In
the prior work cited, the interest was primarily in extended
x-ray response. As noted earlier our interest in a thick CCD
is motivated by improved near-infrared response. Figure 2
shows calculated absorption length in silicon as a function
of wavelength [18]. Absorption length is defined here as
the reciprocal of absorption coefficient α defined in terms
of attenuation of incident light intensity I
0
with depth y,
i.e. I(y)=I
0
e
−αy
.
Given that silicon is an indirect-gap semiconductor, two
regions are of interest. For photon energies above the direct
bandgap energy of 2.5 eV, corresponding to a wavelength of
approximately 500 nm, light absorption is highly efficient
and the absorption coefficient is determined by available
conduction band states [19], [20]. Hence the absorption
coefficient for direct transitions α
d
varies as the square root
of energy as per the energy dependence of the conduction
band density of states, i.e.
α
d
= A
q
hν − E
g,direct
(T )(1)
The temperature dependence is due to the band gap term
E
g,direct
(T ) and is relatively weak in the direct gap regime.
A is a constant, hν is the photon energy, and T is the
absolute temperature.
Below photon energies of 2.5 eV, phonons are required
for momentum conservation and the absorption process be-
comes less efficient and more sensitive to temperature due
to the phonon statistics. In the indirect absorption regime
the absorption coefficient goes as [19], [20]
α
i
=
B(hν − E
g,indirect
+ E
p
)
2
exp(E
p
/kT) − 1
+
B(hν − E
g,indirect
− E
p
)
2
1 − exp (−E
p
/kT)
(2)
where the terms are due to phonon absorption and emis-
sion, respectively. k is Boltzmann’s constant, E
p
is the
phonon energy, and B is a constant. Equation 2 is valid
for photon energies greater than E
g,indirect
+ E
p
while only
the phonon absorption term contributes to the absorption
coefficient for photon energies of E
g,indirect
± E
p
.
The net result is an absorption length that increases
with wavelength as shown in Figure 2. At photon energies
comparable to the indirect bandgap energy the absorption
length can be more than 100 µm, requiring thick CCD’s to
achieve high QE in the near-infrared.
An advantage of a thick CCD fabricated on high-
resistivity silicon is that the CCD clock levels can be set
to optimize performance parameters such as charge trans-
fer efficiency and well depth while the nearly independent
substrate bias is used to achieve full depletion. A one-
dimensional depletion-approximation solution to the Pois-
son equation for a thick CCD with applied substrate bias
is given in Appendix A. The potential V
J
at the buried-
channel/substrate junction is approximately equal to the
potential minimum V
min
and is given by
V
J
≈ V
G
− V
FB
−
qN
A
2
Si
y
J
2
1+
2
Si
d
SiO
2
y
J
(3)
which is independent of the substrate bias voltage V
sub
. V
G
is the applied gate voltage, V
FB
is the flat-band voltage, q
is the electron charge, N
A
is the doping density in the p
channel of depth y
J
, d is the gate insulator thickness, and
Si
and
SiO
2
are the permittivities of silicon and silicon
dioxide, respectively.
This approximation is valid for N
D
N
A
and y
N
y
J
+(
Si
/
SiO
2
) d,wherey
N
is the thickness of the fully-
depleted, n-type region with doping density N
D
(see Fig-
ure 16 in Appendix A). For the CCD’s considered here N
D
is more than four orders of magnitude less than N
A
,and
therefore only a small fraction of the field lines from the
channel are required to terminate in the substrate. Hence
nearly all the field lines from the channel terminate in the
gate, which is the physical interpretation of Equation 3.
The third and fourth terms of Equation 3 are the volt-
age drops across the fully depleted channel and the voltage
drop across the oxide when the channel is fully depleted.
Equation 3 is a one-dimensional approximation to a decid-
edly two-dimensional problem, and it is shown in Appendix
A that the effect of the barrier phases is to slightly raise
the value of V
J
when compared to the 1-d approximation.
However, it is still true that the potential at the junction is
a weak function of the substrate bias due to the large dif-
ference in doping between the channel and substrate and
the use of a thick depleted substrate.
LBNL-49992: Draft for IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 1, 225-338, JANUARY 2003 103
In addition, a thick CCD reduces fringing [21]. In
thinned CCD’s fringing arises due to multiple reflections
at long wavelengths when the absorption length of the in-
cident light is greater than the CCD thickness. Fringing
as well as the loss of QE limits the usefulness of scientific
CCD’s at long wavelengths.
There are several drawbacks to a thick CCD, however.
Charged-particle events from cosmic rays and terrestrial ra-
diation sources will affect more pixels in a thick CCD [22].
Also, a larger volume for near-infrared response implies
more volume for dark current generation and care must be
taken during processing to minimize dark current. In ad-
dition, reduction of surface current due to interface states
is not as straightforward as in a thinned CCD with no sub-
strate bias, although as shown later surface dark current
suppression can be done satisfactorily at cryogenic temper-
atures.
In low-f number optical systems where the light is inci-
dent at large angles from the normal, there will be depth
of focus issues for long-wavelength light absorbed at signif-
icant depths, although the large refractive index of silicon
helps in this regard by “straightening” the light. At the
short wavelength end, the photogenerated holes must tra-
verse nearly the entire thickness of the CCD, and spatial
resolution is a concern. This is discussed in more detail in
Section VI. In the next section the fabrication technology is
described, followed by discussion of transistor behavior of
buried channel MOS devices fabricated on high-resistivity
silicon.
III. CCD Fabrication and Back-Illumination
Technology
The CCD’s discussed in this work were fabricated at
the Lawrence Berkeley National Laboratory Microsystems
Laboratory [3]. The starting material was 100 mm diame-
ter, (100), high-resistivity, n-type silicon manufactured by
Wacker Siltronic.
The gate insulator consists of 500
˚
A of thermally grown
SiO
2
and 500
˚
A of low-pressure chemical vapor deposited
(LPCVD) Si
3
N
4
. The triple polysilicon gate structures are
plasma etched in Cl
2
/HBr for high selectivity to the un-
derlying Si
3
N
4
layer. Single-level Al-Si is used for met-
allization. In-situ doped (phosphorus) polysilicon is used
for extrinsic gettering [6], and this layer is deposited on
the back side of the wafer early in the process and capped
with Si
3
N
4
to eliminate oxidation of the layer and pos-
sible autodoping during subsequent processing. A notch
implant [23] is included in the process and is used in the
serial register to confine small-signal charge packets to a
3 µm wide channel in the serial register, which is wider
than the vertical channel to accommodate binning.
Figure 3 shows an example of a 100 mm diameter wafer
fabricated at LBNL. The large devices in the center of the
wafer are 2048 × 2048, 15 µm pixel CCD’s. The vertical
register is split into two equal regions allowing for frame
store operation, although in most cases the two sets of ver-
tical clocks are connected and the CCD is operated as a
frame transfer device. The serial register located along one
Fig. 3. 100 mm diameter wafer fabricated at LBNL. The two large
CCD’s in the center of the wafer are 2048 × 2048, 15 µmpixel,frame
transfer CCD’s.
side of the CCD is similarly split, allowing for readout to
either amplifier or to both for faster readout rates. The
wafer also includes additional 15 and 24 µm pixel CCD’s.
Since the structure shown in Figure 1 is essentially a
CCD merged with a p-i-n diode, we require a backside
ohmic contact in order to apply the substrate bias needed
to fully deplete the wafer thickness. This ohmic contact
layer must be thin to allow for short-wavelength light trans-
mission. In Figure 2 it can be seen that the absorption
length is less than 0.1 µm for wavelengths less than about
400 nm, and becomes less than 100
˚
A at ultraviolet (UV)
wavelengths.
Previous back-illumination techniques for conventional
scientific CCD’s include UV flooding [24] and laser anneal-
ing of an ion implanted backside layer [13], [25]. In both
cases a built-in field is generated to overcome the native
depletion layer at the backside surface for p-type silicon
due to positive fixed oxide charge at the silicon-SiO
2
inter-
face [1]. Laser annealing is required since the thinning step
is performed on a finished wafer and the annealing temper-
ature of the backside implant is limited to ≈ 475–525
◦
C
depending on the metallization used [26].
Since the devices fabricated on high-resistivity silicon
can be made relatively thick, it is possible to create the
backside layer as a high-temperature step before the Al
is deposited. Bosiers et al. [17] were able to demonstrate
conventional high-temperature annealing of an implanted
backside p
+
layer by virtue of the use of relatively thick
(150 µm and below) high-resistivity substrates that could
be processed through the metallization step after the im-
plant was annealed. Our technique involves removing the
≈ 1 µm thick n
+
polysilicon gettering layer before the con-
tact mask. The wafers are sent to a commercial vendor for
backside polishing to the final desired thickness. Polishing
of the backside surface is required for an optical quality
surface, and in our experience this is especially an issue for
long-wavelength light.
After the polishing step the backside ohmic contact is
formed by depositing a thin (≈ 20 nm) layer of in-situ
doped (phosphorus) polysilicon [27]. This layer is deposited
by LPCVD at 650
◦
C using 1.5% PH
3
in SiH
4
as the source
gas. A sacrificial oxide is then sputtered on the back side
and the wafers are processed through the contact and metal
LBNL-49992: Draft for IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 1, 225-338, JANUARY 2003 104
0 100 200 300 400 500 600 700 800 9001000
Depth (Ångstroms)
Concentration (atoms cm
−3
)
10
21
10
22
10
20
10
19
10
18
10
17
10
16
10
15
Fig. 4. Secondary ion mass spectroscopy depth profile of the thin
back side ohmic contact used in this technology. The layer is fab-
ricated by in-situ doped (phosphorus) polysilicon deposition. The
detection limit for phosphorus was 1 ×10
16
cm
−3
.
steps. During these steps the wafers are thinner than stan-
dard. We have found that 200 - 300 µm thick, 100 mm
diameter wafers can be processed with standard processing
equipment. This becomes more challenging as one scales
to larger diameter wafers. Modification of some automatic
wafer handling equipment was required in order to avoid
damaging the backside surface, as well as to minimize par-
ticle deposition on the back side. In addition, particle re-
moval via scrubbing is used to reduce the final particle
count on the back side of the wafer. If this is not done,
uniformly illuminated images (flat fields) taken in the UV
can show particle patterns from the various wafer handlers
used in the process.
Figure 4 shows a secondary ion mass spectroscopy
(SIMS) depth profile of the phosphorus concentration for a
nominal 200
˚
A thick backside polysilicon film. The detec-
tion limit was 1 ×10
16
cm
−3
and the spatial resolution limit
was 65
˚
A /decade. As can be seen in Figure 4 a very thin
layer is possible with this technique. The peak in the phos-
phorus concentration could be due to phosphorus pile-up at
the original polysilicon-silicon interface resulting from per-
haps a native oxide layer present at that interface [28]. In
general this is not desirable due to the potential for a built-
in field that would oppose hole flow for carriers generated
in the polysilicon layer, although poor collection efficiency
is expected there because of low minority carrier lifetime
due to Auger recombination.
It will be shown later that it is desirable to operate the
CCD over depleted to minimize degradation in spatial res-
olution. In addition, the fairly large radial variation in
resistivity for high-resistivity silicon [29] requires overde-
pleted operation to guarantee the elimination of field-free
regions with correspondingly poor spatial resolution. A
possible concern is the effect on dark current for overde-
pleted operation. Figure 5 shows measured dark current
and inverse square capacitance 1/C
2
measured on 2 mm
2
p-i-n diode test devices. Results are shown from wafers of
3×10
−10
2×10
−10
1×10
−10
0×10
−10
10 150 5 20 25 30 35 40
Substrate bias [V]
Dark current density [A/cm
2
]
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1/C
2
[pF
−2
]
Fig. 5. Inverse square capacitance and reverse leakage current mea-
sured at room temperature on 2 mm
2
p-i-n diode test structures from
CCD wafers. Data are shown for 200 µm (dotted lines) and 275 µm
(solid lines) thick wafers.
0
10
20
30
40
50
60
70
80
90
100
300 400 500 600 700 800 900 1000 1100
Wavelength (nm)
Quantum Efficiency (%)
Fig. 6. Quantum efficiency measured on a 1980 × 800, 15 µm
pixel back-illuminated, fully-depleted CCD. The measurement was
performed at Lick Observatory and the operating temperature was
−130
◦
C. The thickness was ≈ 280 µm.
thickness ≈ 200 and 275 µm. These wafers went through
the entire CCD process. The backside polysilicon thickness
is ≈ 200
˚
A. The dark current at room temperature is less
than 0.2 nA/cm
2
, and does not increase significantly for
bias voltages above that necessary for full depletion, where
the 1/C
2
curves approach a constant level. Therefore the
gettering process is effective in maintaining low dark cur-
rent for large depletion depths, and the thin polysilicon
deposition step does not degrade the dark current.
After the 400
◦
C sintering step the back side sacrificial
oxide is removed and ≈ 600
˚
A of indium tin oxide (ITO)
is deposited [27]. The ITO functions as part of an anti-
reflection (AR) coating and improves the conductivity of
the back side, where an equipotential is desired as described
below. A second AR coating of ≈ 1000
˚
A of SiO
2
is added
to form a 2-layer AR coating optimized for near-IR de-
tection [21]. Figure 6 shows measured QE of an ≈ 280 µm
thick, 1980 × 800, 15 µm pixel back-illuminated CCD with
the two-layer AR coating. The QE exceeds 90% at near-
infrared wavelengths, and is still ≈ 60% at a wavelength of
1 µm. For detailed discussion of QE modeling results for
these CCD’s the reader is referred to reference [21].
As a practical matter it is not convenient to make a di-
rect electrical connection to the back side of the wafer as
shown in Figure 1. Doing so would complicate the use of
LBNL-49992: Draft for IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 1, 225-338, JANUARY 2003 105
0100200
Distance (µm)
0 100 200 300 400 500
Distance (µm)
Grounded p
+
guard ring
Floating p
+
guard rings
V
=
V
sub
(depletion edge)
n
−−
Fig. 7. Two-dimensional simulation of a p-i-n diode structure on
high-resistivity silicon. The equipotential lines are spaced at 1V in-
tervals. The substrate bias voltage was 35V and the substrate doping
and thickness were 4 × 10
11
cm
−3
and 280 µm respectively.
insulating anti-reflecting coatings, for example. Instead, in
the actual implementation the contact is made on the front
side of the CCD. Figure 7 illustrates the technique used to
bias the CCD. Shown in the figure is a two-dimensional
simulation (Medici 4.0.1) of a p-i-n diode structure on a
280 µm thick high-resistivity, n-type substrate. The sub-
strate doping used in the simulation was 4.0 ×10
11
cm
−3
.
For convenience in the simulation the 35 V bias voltage
was applied to the backside ohmic contact. Beyond the
depletion edge the undepleted region is an equipotential at
the applied substrate bias as long as the current flow in
this region is negligible. In that case one can equivalently
place an n
+
contact at the front side of the CCD in the
undepleted region with the same result as shown in Fig-
ure 7, and apply the bias voltage more conveniently there.
The function of the floating p
+
guard rings is to gradu-
ally drop the potential from the undepleted n region to the
grounded p
+
guard ring that surrounds the CCD, thereby
maintaining low electric fields at the surface [30], [31], [32].
Photo-generated electrons are directed by the field in
the fully-depleted substrate to the backside ohmic con-
tact where they flow laterally and are eventually drained
through the undepleted substrate to the front-side n
+
con-
tact located in the undepleted region. For low light level
applications the dc voltage drop in the substrate due to the
electron photocurrent is negligible. A 1 Mpixel CCD oper-
ating at 30 frames/sec with a high light level corresponding
to 100 ke
−
/pixel would have an electron photocurrent of
only ≈ 0.5 µA, for example, while in low level light ap-
plications the photocurrent would be orders of magnitude
smaller. The dc voltage drop in the backside ohmic contact
resulting from lateral drift of electrons along the backside
contact is minimized by the use of the ITO anti-reflecting
layer that has a typical sheet resistance of 40 Ω/square.
This biasing scheme was used in all the results presented
10
−12
10
−11
10
−10
10
−09
10
−08
10
−07
10
−06
10
−05
10
−04
10
−03
9.0 9.5 10.0 10.5 11.0 11.5 12.0
V
gs
[V]
|
I
ds
|
[A]
Fig. 8. Measured subthreshold characteristics of a 47/6 buried chan-
nel PMOSFET with 1.5 µm gate to source/drain spacing. The sub-
strate bias varied from 25V (rightmost curve) to 75V (leftmost curve)
in 10V steps. The temperature was −128
◦
C, and the drain to source
voltage was -1V.
in this paper.
IV. Transistor Performance
The CCD’s described in this work have conventional
floating diffusion amplifiers, and p-channel MOSFET’s are
used for reset and amplification. Given the relatively slow
readout rates, the output source follower is buried channel
to minimize 1/f noise [33], as is the reset transistor. For
process simplicity, the transistors are fabricated directly in
the high-resistivity substrate without the use of a well. We
have found such transistors to give acceptable performance
although future applications could require improvements
in transistor characteristics. Several examples of active de-
vices fabricated directly on high-resistivity silicon for high-
energy physics applications have been reported [34], [35],
[36], as well as early work on MOS transistors fabricated
on high-resistivity silicon [37], [38].
The use of extremely low substrate doping in an MOS
transistor leads to desirable features such as small bulk-
junction capacitance and body effect, as well as undesirable
features such as punchthrough and drain-induced barrier
lowering. The latter two effects can be reduced somewhat
by the application of the substrate bias used to fully deplete
the substrate [3], [35]. In addition, the heavily doped source
and drain regions can be offset from the gate to improve
punchthrough characteristics [39], [40] as well as minimize
overlap capacitance [10].
The small body effect realized for these transistors is
demonstrated in Figure 8, which shows subthreshold char-
acteristics measured on a 47/6 MOSFET with 1.5 µm gate
to source/drain spacing at a temperature of −128
◦
Cfor
substrate bias voltages ranging from 25V to 75V. Over this
50V range in substrate bias the threshold voltage of the
transistor is changed by only ≈ 1.8V, which can easily be
accommodated in the CCD biasing. The data of Figure 8
were measured on a CCD with access to the gate elec-
trode through the reset transistor. The 47/6 transistor is
presently used for most single-stage, source-follower ampli-
fier designs in this technology. The CCD was mounted in a
![Fig. 2. Absorption length versus wavelength for silicon. Data and calculations (dashed lines) are taken from Reference [18]. Additional room temperature data (solid line) is taken from Reference [1].](/figures/fig-2-absorption-length-versus-wavelength-for-silicon-data-1jvyqker.webp)
![Fig. 11. Visible light image of M27 (Dumbbell Nebula) taken with a commercially available, back-illuminated 2048 × 2048, 24 µm pixel CCD. The image was generated from exposures taken at three wavelengths (see text) at the European Southern Observatory 8.2- meter Very Large Telescope (VLT) [42].](/figures/fig-11-visible-light-image-of-m27-dumbbell-nebula-taken-with-t5u222su.webp)