Proceedings ArticleDOI
Reducing power in high-performance microprocessors
Vivek Tiwari,Deo Singh,Suresh Rajgopal,Gaurav G. Mehta,Rakesh Patel,Franklin M. Baez +5 more
- pp 732-737
TLDR
The main trends that are driving the increased focus on design for low power are described and areas that need increased research focus in the future are also pointed out.Abstract:Â
Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is outstripping the benefits of voltage reduction and feature size scaling. Designers are thus continuously challenged to come up with innovative ways to reduce power, while trying to meet all the other constraints imposed on the design. This paper presents an overview of the issues related to power consumption in the context of Intel CPUs. The main trends that are driving the increased focus on design for low power are described. System and benchmarking issues, and sources of power consumption in a high-performance CPU are briefly described. Techniques that have been tried on real designs in the past are described. The role of CAD tools and their limitations in this domain will also be discussed. In addition, areas that need increased research focus in the future are also pointed out.read more
Citations
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Proceedings ArticleDOI
Wattch: a framework for architectural-level power analysis and optimizations
TL;DR: Wattch is presented, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level and opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.
Proceedings ArticleDOI
Dynamic thermal management for high-performance microprocessors
David Brooks,Margaret Martonosi +1 more
TL;DR: This work investigates dynamic thermal management as a technique to control CPU power dissipation and explores the tradeoffs between several mechanisms for responding to periods of thermal trauma and the effects of hardware and software implementations.
Journal ArticleDOI
Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors
David Brooks,Pradip Bose,Stanley Everett Schuster,Hans M. Jacobson,Prabhakar Kudva,Alper Buyuktosunoglu,John-David Wellman,Victor Zyuban,Meeta S. Gupta,Peter William Cook +9 more
TL;DR: The approach of using energy-enabled performance simulators in early design, examining some of the emerging paradigms in processor design and comment on their inherent power-performance characteristics, is described.
Journal ArticleDOI
System-level power optimization: techniques and tools
Luca Benini,Giovanni De Micheli +1 more
TL;DR: This tutorial presents a cohesive view of power-conscious system-level design, which considers systems as consisting of a hardware platform executing software programs, and considers the major constituents of systems: processors, memories and communication resources.
Journal ArticleDOI
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style
TL;DR: The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability and is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously.
References
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Minimizing power consumption in digital CMOS circuits
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Proceedings ArticleDOI
Technology Decomposition and Mapping Targeting Low Power Dissipation
TL;DR: This paper generates a NAND decomposition of an optimized Boolean network such that the sum of average switching rates for all nodes in the network is minimum and performs a power efficient technology mapping that finds an optimal power-delay trade-off value for given timing constraints.
Proceedings ArticleDOI
Technology Mapping for Low Power
TL;DR: This paper focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric, and observes that a significant variation in the power consumption is possible just by varying the choice of gates.
Proceedings ArticleDOI
Technology mapping for lower power
TL;DR: This paper focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric, and observes that a significant variation in the power consumption is possible just by varying the choice of gates.