Journal ArticleDOI
The concept of time-average-frequency and mathematical analysis of flying-adder frequency synthesis architecture
TLDR
This paper attempts to explore and understand the signal characteristics and frequency domain behavior of this architecture through mathematical analysis and the underlying concept associated with this architecture, time-average-frequency, is formally introduced.Abstract:
Flying-adder frequency synthesis architecture is a novel technique of generating frequency on chip. Since its invention, it has been utilized in many commercial products to cope with various difficult challenges. During the evolution of this architecture, the issues related to circuit- and system-level implementation have been studied in prior publications. However, rigorous mathematical treatment on this architecture has not been established. In this paper, we attempt to explore and understand the signal characteristics and frequency domain behavior of this architecture through mathematical analysis. In the meantime, the underlying concept associated with this architecture, time-average-frequency, is formally introduced.read more
Citations
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Journal ArticleDOI
Theory of Flying-Adder Frequency Synthesizers—Part I: Modeling, Signals' Periods and Output Average Frequency
TL;DR: This is a rigorous mathematical theory of the operation of the flying-adder (FA) frequency synthesizer (also called direct digital period synthesizer), and it is shown that the FA behaves differently within different ranges of the frequency word, and the practically useful range is identified.
Journal ArticleDOI
Direct All-Digital Frequency Synthesis Techniques, Spurs Suppression, and Deterministic Jitter Correction
TL;DR: A comprehensive literature review and a comparative study of jitter-correction and spurs-suppression techniques applied to popular direct all-digital frequency synthesis cores, identifying their strengths and weaknesses are presented.
Journal ArticleDOI
Time Moore: Exploiting Moore's Law From The Perspective of Time
TL;DR: This article investigates a more sophisticated strategy to manipulate frequency for clocking an electronic system and proposes an idea of using the rate of switching as a computational variable to encode information, which makes up "Time Moore," which enhances transistors' collective computing capability by using time more efficiently.
Journal ArticleDOI
Clock Technology: The Next Frontier
TL;DR: The difficulties in creating flow-of-time are discussed, the two long-lasting problems in clock generation are identified, and then new challenges in the design of future system are summarized.
Journal ArticleDOI
Exact spectrum and time-domain output of flying-adder frequency synthesizers
TL;DR: The spectrum and time-domain output of the flying- adder frequency synthesizer are derived analytically and the amplitude and phase of the average-frequency component are derived in closed forms.
References
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TL;DR: In this article, a delta-sigma (Delta-Sigma) modulation and fractional-N frequency division technique for indirect digital frequency synthesis using a phase-locked loop (PLL) is described.
Journal ArticleDOI
A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation
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Journal ArticleDOI
A low-noise fast-lock phase-locked loop with adaptive bandwidth control
Joonsuk Lee,Beomsup Kim +1 more
TL;DR: A salient analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status and the phase error amount that achieves fast locking and minimizes output jitters.
Journal ArticleDOI
A multiple-crystal interface PLL with VCO realignment to reduce phase noise
Sheng Ye,L. Jansson,Ian Galton +2 more
TL;DR: In this paper, an enhancement to a conventional integer-N phase-locked loop (PLL) is introduced, analyzed, and demonstrated experimentally to significantly reduce voltage-controlled oscillator (VCO) phase noise.
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