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Proceedings ArticleDOI
02 May 2012
13 Citations
This paper proposes a novel hardened latch design in 90nm CMOS technology.
The separated latch and sensing circuit structure maximizes the performance of latch operation, minimizes power consumption, and improves MTJ lifetime.
This paper proposes an efficient robust latch design in 45 nm CMOS technology.
From this study we show that the final state depends on both initial voltages and latch mismatches.
The equivalent circuit model offers a simple view on latch-up, while 2-D modeling provides more physics and quantitative understanding of latch-up.
The results demonstrate that the proposed SR latch and full adder perform equally well or in many cases better than previous circuits.
Proceedings ArticleDOI
17 Apr 2005
25 Citations
We also propose new latch designs, the best of which is vulnerable only to a single-event, multiple-upset without any delay overhead and consumes only 40% power of a standard latch.
Similar to the conventional M-latch circuit, our proposed M-latches employ two magnetic tunnel junction elements.
The proposed designs demonstrate that the power-delay-product benefit is 13 times on average compared to previous robust latches including standard latch.

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