Showing papers on "Active surface published in 2004"

A Fast Spectral Method for Active 3D Shape Reconstruction

Abstract: Variational energy minimization techniques for surface reconstruction are implemented by evolving an active surface according to the solutions of a sequence of elliptic partial differential equations (PDE's). For these techniques, most current approaches to solving the elliptic PDE are iterative involving the implementation of costly finite element methods (FEM) or finite difference methods (FDM). The heavy computational cost of these methods makes practical application to 3D surface reconstruction burdensome. In this paper, we develop a fast spectral method which is applied to 3D active surface reconstruction of star-shaped surfaces parameterized in polar coordinates. For this parameterization the Euler-Lagrange equation is a Helmholtz-type PDE governing a diffusion on the unit sphere. After linearization, we implement a spectral non-iterative solution of the Helmholtz equation by representing the active surface as a double Fourier series over angles in spherical coordinates. We show how this approach can be extended to include region-based penalization. A number of 3D examples and simulation results are presented to illustrate the performance of our fast spectral active surface algorithms.

Methods and apparatus for packaging integrated circuit devices

Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

Bumped die and wire bonded board-on-chip package

Abstract: An apparatus for making a semiconductor assembly and, specifically, interconnecting a semiconductor die to a carrier substrate. The carrier substrate includes a first surface and a second surface with at least one opening therethrough. The die includes an active surface and a back surface, wherein the die is attached facedown to the first surface of the carrier substrate with conductive bumps therebetween. In addition, a plurality of bond wires is attached through the at least one opening in the carrier substrate between the active surface of the die and the second surface of the carrier substrate. With this arrangement, both the conductive bumps and the bond wires share in the electrical interconnection between the die and the carrier substrate, thereby allowing more space for bond pads to interconnect with bond wires and/or allowing for smaller die sizes.

Semiconductor package with heat spreader

Abstract: A semiconductor package with heat spreader is disclosed. In one embodiment, the semiconductor package comprises a device carrier having a plurality of contact areas and a semiconductor die having a plurality of die pads of an active surface, the semiconductor die being mounted on the device carrier. Connection means to electrically connect the die pads to the contact areas and a heat spreading means mounted on the active surface of the die are provided. The heat spreading means includes an upper plate and a foot ring which protrudes from a bottom surface of the upper plate and which is positioned between the die pads on the active surface such that a cavity is formed between the heat spreading means and the active surface. The cavity is filled with an adhering means interconnecting the heat spreading means and the active surface.

Mounting method of electronic element, manufacturing method of electronic device, circuit board, and electronic equipment

Abstract: PROBLEM TO BE SOLVED: To provide a mounting method of an electronic element in which a mounting structure of high connection reliability can be attained at a low cost by reducing mechanical stress in mounting the electronic element on a wiring board. SOLUTION: An electronic element (semiconductor chip) is bonded onto a wiring board while directing the active surface to the surface side (die bond step). An inclining surface leading to the active surface of the electronic element from the surface of the wiring board is formed around the electronic element (slope forming step). Metal wiring for connecting the electrode terminal on the active surface and the wiring pattern on the wiring board is formed on the inclining surface by liquid drop ejection method (metal wiring formation step). Before the metal wiring is formed, an organic insulating film composed of epoxy resin, urethane resin, or the like, is formed on the active surface of the electronic element on which the metal wiring is formed thus enhancing adhesion. COPYRIGHT: (C)2006,JPO&NCIPI

Electrocatalytic reduction of nitrate on activated rhodium electrode surfaces

Abstract: Electrodeposited rhodium films on titanium substrates have been electrochemically activated to produce a high area surface with a specific activity for nitrate electroreduction directly to N2. The activation process involves oxidation/reduction cycles in an alkaline, KCl electrolyte containing nitrate ions. Surfaces of up to 230 times the geometric area are achieved, together with a surface morphological modification. While the active surface, once formed, is intrinsically unstable during long-term nitrate reduction, its activity can be maintained in situ by an electrochemical cycling procedure. The high area rhodium has the form of a nano-structured ‘sponge’, with a surface area of ca. 19 m2 g−1. The morphological modification is evidenced by a change in the hydrogen UPD structure, changes in the surface redox behaviour associated with OH adsorption, and a reduction in the activation energy for nitrate reduction from ca. 47 to 20 kJ mol−1. The reduction in activation energy, however, is accompanied by a decrease in the pre-exponential factor, and this apparent compensation effect results in similar rate constants on the activated and unactivated surfaces. The enhancement in the catalyst's activity for nitrate reduction results from an increase in the relative activity of nitrate reduction over water reduction. The activated catalyst sustains steady state nitrate reduction at an increased over-potential before the reaction to N2 decays, and hydrogen evolution and reduction to ammonia take place. The presence of nitrate ions is essential for the formation of the active surface, and specifically adsorbed nitrate ions and reductive intermediates are present at the surface when it is reformed. A mechanism for the elementary surface reaction steps involved in nitrate reduction, and the apparent ‘habit’ growth of the active surface phase in the nitrate containing solution is discussed.

Semiconductor device, circuit substrate and electronic instrument

Abstract: A semiconductor device includes a semiconductor substrate with a through hole formed therein, a first insulating film formed inside the through hole, and an electrode formed on an inner side of the first insulating film inside the through hole. The first insulating film at the rear surface side of the semiconductor substrate protrudes beyond the rear surface, and the electrode protrudes on both the active surface side and the rear surface side of the semiconductor substrate. An outer diameter of a protruding portion on the active surface side is larger than an outer diameter of the first insulating film inside the through hole, and a protruding portion on the rear surface side protrudes further beyond the first insulating film to have a side surface thereof exposed. The semiconductor device has improved connectivity and connection strength and, in particular, has excellent resistance to shearing force when used in three-dimensional packaging technology.

Method of constructing a biosensor

Abstract: A method of creating an analyte sensor (10). The method starts with the step of providing an electrochemically active surface (24). Then, at least one nub (22) made of dielectric material and extending transversely outwardly from the electrochemically active surface (24) is created. A curable liquid is applied to the electrochemically active surface and the nub (22) and is then cured. In this process, the nub (22), which could be one of several nubs (22), serves to support the liquid before and during the curing.

Electrochemical Behavior of the Active Surface Layer on Rolled Aluminum Alloy Sheet

Abstract: The highly deformed, micrograined layer on the outermost surface of a rolled Al-Fe-Si-Mn model alloy was electrochemically characterized. The thickness of this deformed surface layer in a 1.0 mm thick sheet was approximately 1 μm. Polarization curves in 5% NaCl solution at pH 3.0 and 11.5 were obtained at different depths from the surface using controlled sputtering in a glow discharge optical emission spectrometer for sample preparation. Both the anodic and the cathodic reactivity of the deformed surface layer were significantly higher than that of the bulk. Consistent with this, image analysis of scanning electron microscopy backscattered images revealed an increased number of fine intermetallic particles in the surface layer as compared with the bulk of the material. The corrosion morphology of the outermost surface was characterized by a high density of fine pits, while fewer and larger pits were observed in the bulk. The results highlight the importance of heavily deformed surface layers in controlling corrosion behavior of rolled aluminum products.

Sardinia Radio Telescope: the new Italian project

Abstract: This contribution gives a description of the Sardinia Radio Telescope (SRT), a new general purpose, fully steerable antenna proposed by the Institute of Radio Astronomy (IRA) of the National Institute for Astrophysics. The radio telescope is under construction near Cagliari (Sardinia) and it will join the two existing antennas of Medicina (Bologna) and Noto (Siracusa) both operated by the IRA. With its large antenna size (64m diameter) and its active surface, SRT, capable of operations up to about 100GHz, will contribute significantly to VLBI networks and will represent a powerful single-dish radio telescope for many science fields. The radio telescope has a Gregorian optical configuration with a supplementary beam-waveguide (BWG), which provides additional focal points. The Gregorian surfaces are shaped to minimize the spill-over and the standing wave between secondary mirror and feed. After the start of the contract for the radio telescope structural and mechanical fabrication in 2003, in the present year the foundation construction will be completed. The schedule foresees the radio telescope inauguration in late 2006.

Photosensitive semiconductor package and method for fabricating the same

Abstract: A photosensitive semiconductor package and a method for fabricating the same are proposed. The package includes a carrier having a first surface, an opposite second surface, and an opening penetrating the carrier; a photosensitive chip having an active surface and a non-active surface, wherein a plurality of bond pads are formed close to edges of the active surface, and the chip is mounted via corner positions of its active surface to the second surface of the carrier, with the bond pads being exposed via the opening; a plurality of bonding wires formed in the opening, for electrically connecting the bond pads of the chip to the first surface of the carrier; a light-penetrable unit attached to the active surface of the chip and received in the opening; and an encapsulant for encapsulating the bonding wires and peripheral sides of the chip to seal the opening.

Method of manufacturing semiconductor device

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which is high in productivity and capable of joining a plurality of semiconductor chips together as the semiconductor chips are made to get less out of position. SOLUTION: First, in Figure (a), a wafer W is placed on a mounting pad 11 as its active surface Wa is kept facing upward. Metal projections 4 each having a tin layer on their tips are formed on the active surface Wa of the wafer W, and a flux 22 is applied on each tip of the metal projections 4. The wafer W contains a plurality of unit regions U corresponding to master chips. In succession, a slave chip 2 equipped with metal projections 5 formed on its active surface 2a is placed on the wafer W by a collet as its active surface 2a is kept facing downward. By this setup, in Figure (b), the metal projections 4 and 5 are temporarily fixed together through the flux 22. The same as mentioned above, the slave chips 2 and 3 are temporarily fixed in the whole unit regions U on the wafer W, and then the wafer W and the slave chips 2 and 3 are heated for a prescribed time at temperatures higher than the melting point of tin. COPYRIGHT: (C)2004,JPO

Method of manufacturing semiconductor device, circuit board, and electronic apparatus

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device wherein the warping of a substrate can be suppressed or removed which comes from a difference in physical constant between the substrate and a functional layer formed on the substrate, and also to provide its manufacturing method, a circuit board, and an electronic apparatus. SOLUTION: The method of manufacturing the semiconductor device having an electrode 34 extended through the substrate 10 comprises processes of forming a concave portion H4 in the active surface of the substrate; forming a first insulation layer on the active surface of the substrate including the inner surface of the concave portion; forming the electrode by filling the inside of the concave portion formed with the first insulation film 22 by a conductor; removing the rear face side of the active surface to expose the electrode and the first insulation film formed in the periphery of the electrode from the rear face of the active surface; and forming, on the rear face of the active surface, a second insulation layer 26 having the same direction for the internal stress as that of the first insulation layer. COPYRIGHT: (C)2006,JPO&NCIPI

Wafer level transparent packaging

Abstract: A process for manufacturing transparent semiconductor packages is disclosed. A wafer having an active surface and a back surface is provided. A plurality of first redistribution lines are formed on the active surface of the wafer to connect the bonding pads of the chips. A transparent polymer is formed over the active surface of the wafer to cover the first redistribution lines. A plurality of first grooves are formed corresponding to the scribe lines and in the back surface of the wafer. Preferably, a back coating is then formed over the back surface to fill the first grooves. Next, a plurality of second grooves are formed corresponding to the first grooves and through the back coating such that the first redistribution lines have exposed portions. A plurality of second redistribution lines on the back coating can extend to the exposed portions of the corresponding first redistribution lines for connecting solder balls on the back surface.

The GBT precision telescope control system

Abstract: The NRAO Robert C. Byrd Green Bank Telescope (GBT) is a 100m diameter advanced single dish radio telescope designed for a wide range of astronomical projects with special emphasis on precision imaging. Open-loop adjustments of the active surface, and real-time corrections to pointing and focus on the basis of structural temperatures already allow observations at frequencies up to 50GHz. Our ultimate goal is to extend the observing frequency limit up to 115GHz; this will require a two dimensional tracking error better than 1.3", and an rms surface accuracy better than 210μm. The Precision Telescope Control System project has two main components. One aspect is the continued deployment of appropriate metrology systems, including temperature sensors, inclinometers, laser rangefinders and other devices. An improved control system architecture will harness this measurement capability with the existing servo systems, to deliver the precision operation required. The second aspect is the execution of a series of experiments to identify, understand and correct the residual pointing and surface accuracy errors. These can have multiple causes, many of which depend on variable environmental conditions. A particularly novel approach is to solve simultaneously for gravitational, thermal and wind effects in the development of the telescope pointing and focus tracking models. Our precision temperature sensor system has already allowed us to compensate for thermal gradients in the antenna, which were previously responsible for the largest "non-repeatable" pointing and focus tracking errors. We are currently targetting the effects of wind as the next, currently uncompensated, source of error.

Electrolyzer cell arrangement

Abstract: Some embodiments of the present invention provide electrolyzer cells in which distribution of water over the surface of an electrolyte layer (e.g. a MEA) is improved. Specifically, some embodiments provide an electrolyzer cell, including a flow field plate arranged in combination with at least two porous metal layers having smooth and flat surfaces, in which water is more uniformly distributed across an active surface of an electrolyte layer, which in turn may lead to a more uniform reaction rate over the active area of the electrolyte layer. Other related embodiments also include simplifications that may reduce costs related to manufacturing and assembly of electrochemical cells.

Semiconductor component and method of manufacture

Abstract: A semiconductor component having a lid for protecting a semiconductor chip and a method for manufacturing the semiconductor component. The semiconductor chip has an active surface and a mounting surface. It is flip-chip mounted to a support substrate so the active surface is adjacent the support substrate. A passive or active circuit element may be mounted to the support substrate. The mounting surface of the semiconductor chip has a radius of curvature. A thermal interface material is dispensed on the mounting surface of the semiconductor chip. A lid is coupled to the support substrate via a lid adhesive. A portion of the lid has a radius of curvature that corresponds to the radius of curvature of the semiconductor chip. A force is applied to the lid so that it contacts the thermal interface material and urges the interface material to the sides of the semiconductor chip. The force causes wetting of the thermal interface material.

Manufacturing method of semiconductor device, semiconductor device, circuit substrate and electronic equipment

Abstract: A method of manufacturing a semiconductor device is provided. The method includes embedding and forming a coupling terminal as an external electrode of an electronic circuit on an active surface side of a substrate having an active surface formed with a plurality of electronic circuits, exposing a part of the coupling terminal by polishing a back surface side of the substrate, mounting a semiconductor chip on the back surface side of the substrate via the coupling terminal, sealing the semiconductor chip mounted on the substrate by a sealing material, and cutting the substrate for every forming area of each electronic circuit and dividing it into a plurality of semiconductor devices.

The surface properties of iron catalyst for ammonia synthesis

Abstract: The reduction process and the surface properties of industrial prereduced triply and doubly promoted iron catalyst for ammonia synthesis have been studied using thermogravimetry, thermal desorption of N2 and X-ray diffraction. The properties of both catalysts have been discussed on the basis of the double layer model of iron catalyst. A concept of facet formation on the active surface of the catalysts has been proposed.

Combined Active-Passive Surface Wave Measurements For Near-Surface Site Characterization

Abstract: Conventional active surface wave measurements performed using a transient or continuous source are often limited in the maximum depth of penetration due to the difficulty of generating lowfrequency energy with reasonably portable sources. This limitation may inhibit accurate seismic site response calculations because of the inability to define deeper structure. By combining measurements of surface waves generated by passive sources including microtremors and cultural noise, it is possible to overcome this problem and develop soil profiles to much larger depths. Passive surface wave measurements are performed using a two-dimensional array of receivers placed in a circular configuration. The frequency range measured during passive testing is often on the order of 1 to 10 Hz. The resulting dispersion curve is combined with the dispersion curve from an active test at the same location using an irregular, linear array. Generally, the passive and active measurements overlap in the frequency range of approximately 4 to 10 Hz and it is necessary to resolve differences between them. Near-field effects on array-based active surface wave methods were studied using numerical simulations for two typical soil conditions. Plots of normalized phase velocity vs. normalized array center capture the effects. The plots of the normalized parameters from the numerical simulation results agree well with the plots from experimental dispersion curves at two sites. Therefore, it may be concluded that the differences between the active and passive dispersion curves at low frequencies result from errors caused by near-field effects. It is recommended that a composite dispersion curve be obtained by using only passive dispersion data at low frequencies. The composite dispersion curve is then inverted to obtain the shear wave velocity profile. The proposed procedure is illustrated at two sites in Memphis, Tennessee and San Jose, California.

Method of production of multilayer circuit board with built-in semiconductor chip

Abstract: A method of production of a multilayer circuit board comprised of a multilayer structure circuit formed by a plurality of interconnect layers and insulation layers stacked together and a semiconductor chip included therein, including the steps of placing a semiconductor chip having a polished back surface, with its active surface facing downward, on an already formed lower interconnect layer and forming an insulation layer over the layer on which the semiconductor chip has been placed, the method further including the step of treating the polished back surface of the semiconductor chip to improve its bondability with the insulation layer before the step for formation of the insulation layer

Method of backside grinding a bumped wafer

Abstract: A method for backside grinding a bumped wafer is disclosed. A wafer has a plurality of bumps formed on the active surface thereof. Prior to grinding the back surface of the wafer, a hot-melt adhesive layer is formed on the active surface of the wafer so as to be adhered to the active surface and cover the bumps. Also a grinding film is attached to the hot-melt adhesive layer. After grinding the back surface of the wafer, the grinding film is removed but the hot-melt adhesive layer is remained on the wafer for the following wafer-dicing step.

Image sensor package and method for manufacturing the same

Abstract: An image sensor package includes a substrate, a chip, a transparent cover, and a lens module. The substrate has an upper surface and a lower surface, and has a plurality of connection pads disposed on the lower surface and a though opening. The chip has an active surface, and has an image sensor disposed on the active surface, corresponding to the through opening of the substrate. Also and, a plurality of bumps are disposed at peripheral region of the active surface and are electrically connected to the pads. The transparent cover is disposed in the through opening of the substrate and covers the image sensor. The lens module is disposed on the upper surface for transmitting light to the image sensor.

Apparatus and method for miniature semiconductor packages

Abstract: A method and apparatus for making reliable miniature semiconductor packages having a reduced height and footprint is provided. The package includes a semiconductor chip having an active surface and a non-active surface and one or more contacts positioned adjacent the semiconductor chip. Electrical connections are formed between the contacts and the semiconductor chip. An adhesive tape provided adjacent the non-active surface of the semiconductor chip and the one or more contacts positioned adjacent the semiconductor chip. An adhesive material provided between the non-active surface of the chip and the adhesive tape.

Novel medical electrode configurations

Abstract: A medical electrode includes an active surface extending from a first end to a second end and has a maximum outer diameter exceeding an outer diameter of the both the first end and the second end. The electrode further includes a recess formed in the active surface and an agent held in the recess and adapted to disperse out from the recess upon implantation of the electrode.

Semiconductor device and its manufacturing method, circuit board, and electronic equipment

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing short-circuiting between the signal line and the ground when laminating SOLUTION: The semiconductor device comprises a semiconductor substrate 10 on which an integrated circuit is formed, an electrode 34 formed inside a through hole H4 formed from an active surface 10a to a rear surface 10b in the semiconductor substrate 10 via a first insulating layer 22, and a second insulating layer 26 formed on the rear surface 10b of the semiconductor substrate 10 Then, the electrodes 34 of a plurality of semiconductor chips 2 are mutually connected via a solder layer 40, thus composing the three-dimensionally packaged semiconductor device COPYRIGHT: (C)2005,JPO&NCIPI

Semiconductor device, method of manufacturing same, circuit board, and electronic apparatus

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which is equipped with through-electrodes to achieve three-dimensional mounting and more decreased in size and thickness, to provide a method of manufacturing the same, and to provide a circuit board and an electronic apparatus equipped with the same SOLUTION: The semiconductor device 1 is equipped with a semiconductor substrate 10, its active surface 10A provided through the semiconductor substrate 10 and equipped with an integrated circuit, and through-electrodes 12 protruding from the backside 10B of the semiconductor substrate 10 A first resin layer 18 is provided on the active surface 10A of the semiconductor substrate 10, set thicker than the height of a part of the through-electrode 12 protruding from the active surface 10A, and openings that make, at least, parts of the through-electrodes 12 exposed to the outside Wiring layers 21 provided on the first resin layer 18 and connected to the through-electrodes 12 through the intermediary of the openings respectively and external connecting terminals 23 connected to the wiring layers 21 are provided COPYRIGHT: (C)2006,JPO&NCIPI

Multi-chip package

Abstract: A multi-chip package is provided A first die pad has a first chip attaching surface and a first unoccupied surface A second die pad has a second chip attaching surface and a second unoccupied surface The connecting structures are used for connecting the first die pad and the second die pad The inner leads has wire connecting surfaces The wire connecting surfaces, the first chip attaching surface and the second unoccupied surface face the same direction A first chip has a first active surface and a first inactive surface The first inactive surface is attached to the first chip attaching surface A second chip has a second active surface and a second inactive surface Part of the second active surface is attached to the second chip attaching surface The wires are used for electrically connecting the first active surface and the second active surface to the wire connecting surfaces

Stacked-die extension support structure and method thereof

Abstract: A structure includes a substrate having a first surface, a first semiconductor die, a spacer and a second semiconductor die. The first semiconductor die has an active surface with opposite first and second parallel rows of bond pads, and an opposite inactive surface attached to the first surface of the substrate. The spacer is coupled to the active surface of the first semiconductor die entirely within the first and second rows of bond pads of the first semiconductor die, the spacer overhanging at least one side of the first semiconductor die. The second semiconductor die has an active surface and an opposite inactive surface, the active surface of the second semiconductor die larger in area than the active surface of the first semiconductor die, the active surface of the second semiconductor die with at least one row of bond pads.