Showing papers on "Adder published in 1988"

Fault-tolerant FFT networks

Abstract: Two concurrent error detection (CED) schemes are proposed for N-point fast Fourier transform (FFT) networks that consists of log/sub 2/N stages with N/2 two-point butterfly modules for each stage. The method assumes that failures are confined to a single complex multiplier or adder or to one input or output set of lines. Such a fault model covers a broad class of faults. It is shown that only a small overhead ratio, O(2/log/sub 2/N) of hardware, is required for the networks to obtain fault-secure results in the first scheme. A novel data retry technique is used to locate the faulty modules. Large roundoff errors can be detected and treated in the same manner as functional errors. The retry technique can also distinguish between the roundoff errors and functional errors that are caused by some physical failures. In the second scheme, a time-redundancy method is used to achieve both error detection and location. It is sown that only negligible hardware overhead is required. However, the throughput is reduced to half that of the original system, without both error detection and location, because of the nature of time-redundancy methods. >

Chaos in digital filters

Abstract: It is shown that when the second-order digital filter is implemented using a two's-complement arithmetic for the addition operation, it can exhibit chaotic behavior for certain regions in the parameter space. The overflow nonlinearity of the adder results in a rather complex dynamics, with a phase portrait that is self-similar and has a fractal geometry. The intricate chaotic dynamics of this nonlinear filter is analyzed using symbolic dynamics involving three symbols. >

Image signal processing apparatus

Abstract: PURPOSE:To display the two-dimensional characteristics of the color components of an image in real time, by extracting the change of the desired color component of a video signal to output the same in the state superposed on the original signal. CONSTITUTION:The component signals R, G, B of the RGB signal inputted from a video signal input terminal 31 are inputted to M-bit gradation boundary line detection circuits 32R, 32G, 32B to be converted to M-bit gradation data. These converted gradation data detect the timings transferring to other gradations to output gradation boundary line detection signals 33R, 33G, 33B. The R-, G- and B-boundary line signals 37R, 37G, 37B of a logical operation circuit 36 are inputted to a video level converting circuit part 41 formed from video level converting circuits 41R, 41G, 41B and respectively added to the primary color signals R, G, B by the adder circuits 42R, 42G, 42B forming an adder circuit part 42 to be outputted from video signal output terminals 43.

Anti-aliasing raster operations utilizing sub-pixel crossing information to control pixel shading

Abstract: A method and apparatus for performing anti-aliasing of rendered lines, text and images displayed by a workstation on a video display. The anti-aliasing is performed by logically dividing each addressable frame buffer pixel into sixteen sub-pixels and generating a gray scale value for the displayed pixel that is a function of the number of sub-pixels crossed by a portion of a rendered image. The invented circuitry is part of the circuitry used for combining source and destination data which forms the displayed image namely, an anti-aliasing mask and filter, adder/subtractor logic, saturation logic and anti-aliasing logic.

Efficient use of time and hardware redundancy for concurrent error detection in a 32-bit VLSI adder

Abstract: The adder is intended to be used as a building block in the design of more complex circuits and systems using very large scale integration (VLSI). An efficient approach to error detection has been selected through extensive comparisons of several methods that use hardware, time, and hybrid redundancy. Simulation and analysis results are presented to illustrate the adder's timing characteristics, hardware requirements, and error-detection capabilities. One novel feature of the analysis is the introduction of error latency as a means of comparing the error-detection capabilities of several alternative approaches. >

A multiplier chip with multiple-valued bidirectional current-mode logic circuits

Abstract: A description is given of a 32*32-bit signed digit multiplier implemented with multiple-valued, bidirectional, current-mode circuits and based on two-microcomputer complementary metal-oxide-semiconductor technology. The multiplier can perform 32-bit two's-complement multiplication with three-stage SD full adders using a binary-tree addition scheme The effective multiplier size in the chip and the power dissipation are almost half that of the corresponding binary CMOS multiplier. The multiply time is comparable to that of the fastest binary multiplier. These results establish the effectiveness of the technology for future very large scale integration. >

Variants of an improved carry look-ahead adder

Abstract: An improved variation on the carry look-ahead adder has been proposed by H. Ling (IBM J. Res. Develop., vol.25, p.156, May 1981). Ling's approach is based on the propagation of a composite term in place of the conventional look-ahead carry. This approach gives an adder that is faster and less expensive. In the present study, Ling's adder is introduced and described in a general manner in order to expose the essence of his approach. From this reformulation, it is shown that there are many such variations on the carry look-ahead adder, a few of which share the desirable properties of Ling's adder. >

Embedding computation in one-dimensional automata by phase coding solitons

Abstract: It is shown that some kind of meaningful computation can be embedded in very simple, microscopically homogeneous, one-dimensional automata, and in particular filter automata with a parity next-state rule. A systematic procedure is given for generating moving, periodic structures (particles). These particles exhibit soliton-like properties; that is, they often pass through one another with phase shifts. Ways to encode information in the phase of these particles are discussed. The search for useful logical operations is reduced to a search for paths in certain graphs. As a demonstration of principle, the details of implementing a carry-ripple adder are given. >

Module selection for pipelined synthesis

Abstract: Module selection is one of the many functions which have to be performed during behavioral synthesis of pipelined designs. Module selection is the process of choosing the types of modules (e.g. carry-look-ahead adder) to implement each operation (e.g. addition). In this paper, we give a limited solution to the module selection problem for pipelined designs. A model for estimating area-time tradeoffs [3] for pipelined designs is used to formulate the module selection problem, and an overview of the solution technique is given. Complexities introduced by non-optimal designs and user constraints are also addressed. The results have been validated using designs generated by an automated pipeline synthesis program.

Parallel architecture modified Booth multiplier

Abstract: The paper describes a novel implementation of the modified Booth algorithm in which groups of the partial product terms are summed in parallel and these partial results are then combined in a Wallace tree adder array. The final output is formed by an accelerated carry adder. An extension of the scheme from unsigned binary arithmetic to 2's complement is also described. A 16-bit version of the architecture has been modelled in Pascal and Ella to validate its operation for use in a systolic array DSP chip.

Pipeline-type serial multiplier circuit

Abstract: A pipeline-type serial multiplier having a cellular structure, each cell comprising an adder which operates on 3 one-bit data x, y, c and which determines the result v modulo 2 and the carry co of the addition of x, y, and c. Each adder simultaneously determines a data c1 which is the modulo 2 result of the addition of x, y, co. This enables the exact final result of a multiplication of a data A of n bits by a data B of p bits to be obtained in two successive segments: a segment L which is formed by the p bits of lowest digital weight and a segment H which is formed by the n bits of the highest weight. The output rate is F/n, where F is the clock frequency. The multiplier circuits can be cascaded under the control of an external signal. They can also be connected in parallel in order to add the results of two multiplications.

Digital filter for a modem sigma-delta analog-to-digital converter

Abstract: Digital filter used in a sigma-delta decoder wherein each input sample is involved in the computation of three consecutive pulse coded modulation (PCM) output samples. During one sigma-delta sampling period, the filter performs three parallel operations by multiplexing one adder running three times faster than the sigma-delta clock for loading one of three accumulators. As the analog-to-digital converter must be kept in phase with remote modem transmit clock, the PCM sampling clock is controlled by the phase tracking performed by adding or subtracting one period of the crystal oscillator from time to time to the PCM sampling clock period. Rotating the order in which the accumulators are loaded by the adder each PCM sampling time enables having zero as the last coefficient value to add to the accumulator, the contents of which is used as PCM output samples. Thus, each PCM sample value is available in the corresponding accumulator one sigma-delta clock period before the last computation. In case of a correction which shortens or lengthens the PCM sampling period, this correction does not change the PCM sample value to be output since the last computation which is either cancelled or repeated, consists in adding zero to the previous accumulator contents.

Four-to-two adder cell for parallel multiplication

Abstract: A four-to-two adder for adding four numbers and generating two numbers which has the same sum as the sum of the four input numbers is used to add partial products in a multiplier. A plurality of adder cells are arranged in parallel to process corresponding bits of the four numbers. Each adder cell couples three of the four input bits to the next stage. A four-bit parity circuit is used to control two multiplexers which select signals from a carry generator and the one input signal which is not coupled to the subsequent adder cell stage to provide two output bits corresponding to the two output numbers.

Efficient design of totally self-checking checkers for all low-cost arithmetic codes

Abstract: A method is proposed that is based on the partitioning of the input code variables into two sections, each section representing the binary form of a number Z/sub 1/ and Z/sub 2/, respectively. For a code with check base A=2/sup m/-1, two m-bit end-around carry adder trees calculate the modulo m residue of Z/sub 1/ and Z/sub 2/, while a totally self-checking (TSC) translator maps the output of the pair of trees onto m-variable two-rail code. A TSC two-rail checker maps the m-variable two-rail code onto one-out-of-two code. The checkers present significant improvement in the implementation cost, number of gate levels, and reliability over TSC checkers previously proposed in the literature. >

Optical arithmetic/logic unit based on residue arithmetic and symbolic substitution.

Abstract: There has been difficulty in achieving a fully parallel, digital optical adder or multiplier. The primary obstacle is the carry operation inherent in any fixed-radix number system. The concepts of residue number representation and symbolic substitution can be combined to produce a parallel optical arithmetic/logic unit.

Efficient testing of optimal time adders

Abstract: Considers the design of two well-known optimal time adders: the carry look-ahead adder and the conditional sum adder. It is shown that 6 log/sub 2/(n)-4 and 6 log/sub 2/(n)+2 test patterns suffice to completely test the n-bit carry look-ahead adder and the n-bit conditional sum adder with respect to the single stuck-at fault model (for a given set of basic cells). The results are considered pertinent to establishing the correct behavior of a given VLSI chip. >

Gain-variable amplifier circuit

Abstract: A variable gain amplifier for compensating for an amplitude frequency response characteristic of an input signal transmitted through a transmission path having a predetermined attenuation characteristic, includes a first amplifier for amplifying the input signal with a substantially flat amplitude frequency response characteristic, a second amplifier for amplifying the input signal with a predetermined amplitude frequency response characteristic corresponding to the attenuation characteristic of the transmission path, an adder circuit for reciprocally level-controlling the signals amplified by the first and second amplifiers so that a level of one of the signals is increased when a level of the other signal is reduced, and adding the level-controlled signals to each other, and an addition controller for variably setting a determination amount of level control performed by the adder circuit in accordance with a line length of the transmission path.

East image processing accelerator for real time image processing applications

Abstract: A modular matrix processor which is capable of configuration as a stand alone symmetrical kernel convolutor or one of plural cascaded asymmetrical kernel convolutors. The module includes coefficient registers and associated multipliers to multiply sequential pixels or words by an appropriate coefficient. A summer, with appropriate input delays, sums the products and provides them to a plurality of FIFO (first in - first out) for storing the sums per row. An adder adds the contents of the summer, FIFO's and cascaded inputs to provide a convolution output Pc. Plural frames may be processed using the pixel input, coefficient input and cascade inputs. Plural modules may be used per row to increase the kernel size as well as the row capacity of the FIFO's.

Approaching a nanosecond: a 32 bit adder

Abstract: The authors describe a high performance 32-bit binary adder designed at Stanford University. Measurements indicate that the adder computes the sum of two numbers (and a carry) in 2.1 ns and consumes 900 mW, using a power-supply voltage of -4.5 V. The adder is implemented using silicon emitter-coupled-logic circuitry with 0.5-V output swings. The high performance is a result of high-speed logic/technology and a special addition algorithm which results in an adder with a maximum of three levels of logic from any input to any output. The maximum fanout on any signal is eight input loads, the maximum number of inputs on any gate is five, and the maximum number of WIRE-OR outputs is eight. >

Method and apparatus for implementing binary multiplication using booth type multiplication

Abstract: In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recoded into 3-bit groups The corresponding partial product terms are reduced in a regular array of small carry-save adder cells Iterative use of the CSA array provides the Wallace tree function in one-seventh the chip area or number of adders of a conventional implementation The multiplier is pipelined internally, driven by a fast, two-phase internal clock that is transparent to the user The internal clock stops and restarts upon loading new operand and instruction data to synchronize the internal clock to the system clock Other aspects of the invention include high-speed absolute value subtract circuitry for exponent calculations and normalizing floating point results

Apparatus and method for floating point normalization prediction

Abstract: The invention is directed to an apparatus and method for predicting the number of bits which must be taken into account to normalize the result of a floating point addition or subtraction. The apparatus and method employ: a low precision floating point adder/subtractor, a priority encoder that determines the position of the most significant non-zero bit to generate the normalization amount and preround logic which pre-shifts a rounding bit in the opposite direction of normalization. The method and apparatus operate in parallel with a full precision floating point adder to eliminate the need for a full-precision floating point normalization calculation and rounding computation in most circumstances. The normalization amount for successful low-precision floating-point addition/subtraction is calculated by the time the full-precision floating-point addition/subtraction stage occurs. Moreover, the pre-round logic supplies a carry bit to the full-precision adder/subtractor thus saving the time associated with a full-precision rounding bit addition. Thus, this low-precision floating-point addition/subtraction technique results in a significant enhancement of performance in floating-point addition/subtraction.

Method and apparatus for modified carry-save determination of arithmetic/logic zero results

Abstract: The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.

iCOACH: a circuit optimization aid for CMOS high-performance circuits

Abstract: iCOACH is a two-pass iterative circuit optimizer which generates a polycell-based layout from a gate-level description file and user-defined timing constraints The first pass is to place and route the cells and extract the interconnection parameters The second pass optimizes the circuit at the transistor level and makes necessary pitch-matchings Although iCOACH has a layout style similar to the polycell approach, it is distinct in two important aspects First, iCOACH does not rely on any fixed cell library Instead it generates customized cells by invoking the circuit optimizer and performs the transistor-level optimization for both static and dynamic CMOS circuits Second, although the cells in the same row are required to have the same height, different rows can have different heights to make circuit more compact Dynamic circuits are considered, with a careful treatment of reliability issues related to charge sharing and noise margin A novel polycell layout style for dynamic CMOS circuits is introduced A 4-bit ALU and a 32-bit adder are used to demonstrate the capability of iCOACH >

Circuit for cancelling whole or part of a waveform using non-recursive and recursive filters

Abstract: The whole or part of a waveform is cancelled by a circuit comprising a nonrecursive filter (10) and a re­cursive filter (11,12). The nonrecursive filter (10) has a plurality of first multipliers (17-0 to 17-(N-1)) having first tap weights for modifying symbols successively shift­ed along a shift register (13-O to 13-N). The recursive filter (11,12) is connected in a series circuit to the shift register and has a second tap weight for recursively modifying the output of the shift register. The recursive­ly modified symbol is modified by a second multiplier (16-O to 16-(N-1)) having a third tap weight and combined in an adder (18) with the symbols modified by the first tap weights to produce a replica of an undesired waveform. The replica is destructively combined in a subtractor (19) with an in­coming symbol having an undesired waveform. The output of substractor (19) is utilized to derive the tap weights to adaptively control the inputs to the adder.

A single chip parallel multiplier by MOS technology

Abstract: A parallel multiplier design based on the five-counter cell is discussed. A design optimization for the performance in speed is proposed at the logic design level which is developed into an MOS circuit design. The comparison of the five-counter cell design and the full adder cell design reveals that the proposed design is most useful with pass gate logic and results in high-speed multiplication (approximately twice as fast as that of the full adder design) with a moderate increase in hardware complexity. With the five-counter design, an improvement in the hardware complexity of a squarer can be expected. >

BCD adder circuit

Abstract: The binary coded decimal (BCD) adder circuit for adding two BCD encoded operands and for producing a BCD encoded sum includes a bank of parallel full adder circuits as a first stage which generate an intermediate sum vector and an intermediate carry vector from the sum of the operands and a precorrection factor. A second stage of the BCD adder circuit includes carry lookahead adder circuitry receiving as inputs the intermediate sum vector and the intermediate carry vector and producing a propagate vector and a final carry vector. The third stage of the BCD adder circuit conditionally modifies the propagate vector to form the BCD encoded sum according to bits of the intermediate carry vector and the final carry vector as inputs.

A GaAs 4-bit adder-accumulator circuit for direct digital synthesis

Abstract: A GaAs depletion-mode MESFET integrated circuit which is implemented with buffered FET logic and contains 155 gates is described. The chip is composed of a 4-bit adder, a 4-bit register, and lookahead-carry logic capable of connecting up to four chips in a 16-bit parallel adder-accumulator circuit for direct digital synthesis of a sinewave. Fully functional chips have been fabricated by a GaAs foundry. Design rules were conservatively set to 1.5- mu m FET gate lengths. In synchronous operation without clock skew, a 16-bit four-chip configuration was breadboarded and operated at clock frequencies up to 200 MHz. Both a 4-bit one-chip breadboard and an 8-bit two-chip breadboard operated at clock frequencies up to 340 MHz. Chip power dissipation is approximately 500 mW including pad driver circuits. A next-generation pipelined adder-accumulator design based on the experience gained with this chip design is presented. For the LSI pipelined design with 1- mu m gate length, maximum clock speed is projected as 800 MHz to 1 GHz. >

Error-correcting codes for a T-user binary adder channel

Abstract: A construction is given which allows error correction of a code for the T-user binary adder channel with two codewords per user. The construction for a noisy channel is generalized to allow a greater freedom in choosing the parameters of the code without decreasing the rate sum. An example which illustrates an efficient decoding algorithm for the noisy channel is given. >

Digital multiplier circuit and a digital multiplier-accumulator circuit which preloads and accumulates subresults

Abstract: Disclosed is a digital multiplier-accumulator circuit utilizing a carry save adder tree, pipeline register and carry select adder. Also disclosed is a digital multiplier circuit including a carry save adder tree and a pipeline register.