Showing papers on "Analog-to-digital converter published in 1999"

Analog-to-digital converter survey and analysis

Abstract: Analog-to-digital converters (ADCs) are ubiquitous, critical components of software radio and other signal processing systems. This paper surveys the state-of-the-art of ADCs, including experimental converters and commercially available parts. The distribution of resolution versus sampling rate provides insight into ADC performance limitations. At sampling rates below 2 million samples per second (Gs/s), resolution appears to be limited by thermal noise. At sampling rates ranging from /spl sim/2 Ms/s to /spl sim/4 giga samples per second (Gs/s), resolution falls off by /spl sim/1 bit for every doubling of the sampling rate. This behavior may be attributed to uncertainty in the sampling instant due to aperture jitter. For ADCs operating at multi-Gs/s rates, the speed of the device technology is also a limiting factor due to comparator ambiguity. Many ADC architectures and integrated circuit technologies have been proposed and implemented to push back these limits. The trend toward single-chip ADCs brings lower power dissipation. However, technological progress as measured by the product of the ADC resolution (bits) times the sampling rate is slow. Average improvement is only /spl sim/1.5 bits for any given sampling frequency over the last six-eight years.

A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter

Abstract: A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.

An 8-bit 150-MHz CMOS A/D converter

Abstract: This paper describes an 8-bit 5-stage pipelined and interleaved analog-to-digital converter that performs analog processing only by means of open-loop circuits such as differential pairs and source followers to achieve a high conversion rate. The concept of sliding interpolation is proposed to obviate the need for a large number of comparators or interstage digital-to-analog converters and residue amplifiers. The pipelining scheme incorporates distributed sampling between the stages so as to relax the linearity-speed tradeoffs in the sample-and-hold circuits, A clock edge reassignment technique is also introduced that suppresses timing mismatches in interleaved systems, and a punctured interpolation method is proposed that reduces the integral nonlinearity error with negligible speed or power penalty. Fabricated in a 0.6-/spl mu/m CMOS technology, the converter achieves differential and integral nonlinearities of 0.62 and 1.24 LSB, respectively, and a signal-to-(noise+distortion) ratio of 43.7 dB at a sampling rate of 150 MHz. The circuit draws 395 mW from a 3.3-V supply and occupies an area of 1.2/spl times/1.5 mm/sup 2/.

Realizing analog-to-digital converter on a digital programmable integrated circuit

Abstract: An analog-to-digital converter (ADC) is realized in a field programmable gate array (FPGA) without adding special dedicated analog circuitry. In a digital application, a comparator in an interface cell of the FPGA compares an incoming digital signal to a reference voltage. Adjusting of the reference voltage allows the interface cell to support different digital I/O standards. In one embodiment, the comparator is not used for this digital purpose, but rather is used as a comparator in an ADC. A flash ADC is realized by using the comparators of numerous interface cells as the comparators of the flash ADC. Conversion speed is increased by reducing the impedance of the analog signal input path. An on-chip resistor string is provided so that the flash ADC can be realized without external components. In another embodiment, the comparator of the interface cell is the comparator of a successive approximation ADC. In some embodiments, an interface cell has a pad that is usable for receiving a digital signal or for receiving an analog signal. The interface cell includes special dedicated analog circuitry that has a differential input lead that is programmably couplable to the pad.

Multi-loop SIGMA DELTA analog to digital converter

Abstract: A bandpass SIGMA DELTA DC utilizing either a single-loop or a MASH architecture wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, or a two-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a SIGMA DELTA ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 SIGMA DELTA ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass SIGMA DELTA ADC can also be used in conjunction with undersampling to provide a frequency downconversion.

Delta-sigma oversampled ultrasound beamformer with dynamic delays

Abstract: The principles of oversampling are exploited in a simple beamforming architecture using a single bit delta-sigma (/spl Delta/C) analog to digital converter (A/D) on every channel. The high sampling rate required for the single bit A/D provides adequate delay accuracy for high quality beamforming using elementary sample manipulations. Images produced with this beamformer exhibit significant artifacts directly related to dynamic focusing. However, a simple digital recording technique following delays permits dynamically focused beamforming without degrading image quality. The simplicity of this beamformer compared to conventional methods may facilitate very large channel count or low power beamformers suitable for 1.5-D arrays or portable scanners.

Analog-to-digital converter having voltage to-time converter and time digitizer, and method for using same

Abstract: A single slope A/D converter utilizes a sub-nanosecond time digitizer to achieve increased conversion rates independent of a high frequency clock, and so is capable of being implemented in diverse applications. High conversion rates ranging from about 3 MHz to about 12 MHz and higher may be implemented on integrated circuits without using a high frequency clock.

Autoranging analog to digital conversion circuitry

Abstract: An autoranging analog to digital conversion system is provided. The system may include a digitally programmable preamplifier for amplifying a difference between an analog input and an estimate of the analog input. The preamplifier may be coupled to an analog to digital converter for converting the preamplifier output to a digital signal. The system may also include digital domain predictor or estimation logic for determining an optimum gain and analog input estimate for a given analog input. Multiple signal input channels may be coupled to the analog to digital conversion system. The autoranging estimations may be performed on a sample by sample basis or a channel by channel basis.

Two-stage pipelined recycling analog-to-digital converter (ADC)

Abstract: An Analog-to-Digital Converter (ADC) contains two pipeline stages that operate in parallel on two different analog samples. Each pipeline stage includes two sub-stages. Each sub-stage has a low-resolution ADC element and a low-resolution DAC element. The ADC element converts the analog voltage input to the sub-stage into B digital bits, where B is a low number such as 1, 1.5, or 2. These digital bits are re-converted back to an analog DAC voltage by the DAC element. A subtractor then subtracts the analog DAC voltage from the sub-stage's analog input voltage to produce a difference voltage that represents the quantization error of the ADC/DAC elements. A multiplying amplifier multiplies the difference voltage by 2 B to generate an output voltage to the next sub-stage. Each high-level pipeline stage acts as a recycling ADC, having a feedback switch that connects the output of the last sub-stage to the analog input of the first sub-stage. During successive clock periods, the first sub-stage converts B digital bits during a PH 1 phase while the last sub-stage converts another B digital bits of less significance during the PH 2 phase. The analog output from the last sub-stage is recycled back to the first sub-stage for the next clock and another 2B bits are converted in the next clock period. Once all of the MSB's have been converted, the last sub-stage outputs an analog residue voltage to the first sub-stage of the second pipeline stage, which then converts the LSB bits over several clock cycles using the same recycling method.

User transparent self-calibration technique for pipelined ADC architecture

Abstract: A user transparent self-calibration technique for an analog to digital converter is described. The technique can correct for capacitor mismatch error with minimal additional power consumption. This is done by generating a calibration signal, one for each capacitor whose calibration is desired. The signal is interleaved with the input signal, and digitized by alternating with the input signal digitization using capacitor arrays.

Measurement and compensation system for thermal errors in machine tools

Abstract: A measurement and compensation system for thermal errors in a machine tool is disclosed. A module is provided to compensate thermal errors of the machine tool. The module comprises an operating part, a data bank, an analog to digital converter, a counter and a digital input/output part. The data bank stores in all the coefficients applied to a thermal error modeling equation which governs a relation between temperatures and thermal errors at various operating conditions. The operating part determines all the coefficients of the thermal error modeling equation which are stored in the data bank and calculates the thermal errors corresponding to the temperatures of a plurality of the thermocouples by the temperatures of a plurality of thermocouples inputted from the A/D converter and the positional coordinates of the bed inputted from the counter. Then, digital data of the calculated thermal errors are inputted into the digital input/output part and the digital input/output part converts the digital data to digital signal to input the digital signals into the controller. A controller orders the machine tool to compensate the thermal errors at the positional coordinates of the bed and the feed of the spindle. Accordingly, since the machine tool compensates the thermal errors in advance, the machine tool processes precisely workpieces in spite of the occurrence of the thermal errors.

Embedded mechanism offering real-time self failure detection for an analog to digital converter

Abstract: This invention describes a real-time failure detection system for the inputs of an analog-to-digital converter. A novel mechanism is proposed that provides recognition of an ADC input pin failure through the digital result obtained. The device includes a specific hardware architecture which can be added to any ADC core. This is especially useful in safety applications (where FMEA is a main concern), as it greatly increases the reliability of the analog data measured.

Techniques for converting a plurality of channels continuously in an A/D converter

Abstract: A method and apparatus are used to continuously convert a plurality of analog signals on a corresponding plurality of physical channels using a circuit having analog to digital converter (ADC) components, a serial port interface, and a serial port controller. Logical channel information for one or more logical channels is stored in a register on the serial port controller. Each logical channel specifies one of the physical channels and conversion information for controlling the ADC components to produce a digital sample of the analog signal on the specified physical channel. At least one looping bit and at least one depth bit are also stored in a register on the serial port. The depth bit indicates a number of logical channels in one data scan. At least that number of logical channels are stored in the register. In response to a command bit indicating conversion mode, a quantity of data scans is output on a serial output pin of the serial port interface. Each data scan includes a number of data words equal to the number of logical channels in a scan. Each data word includes one digital sample specified by a corresponding one of the number of logical channels. The quantity of scans is responsive to the value stored in the looping bit or bits.

Digital imaging control with selective intensity resolution enhancement

Abstract: Image enhancement is automatically achieved by calibrating the reference voltage and gain of a differential amplifier and the integration interval so as to provide an input to a differential analog to digital converter (ADC) that utilizes the full dynamic range of the ADC. When used with a CMOS array, the imaging logic can be fabricated on a single chip with the array using combinational logic for fast, inexpensive calibration. Another advantageous feature is the ability to expand a desired portion of the luminance spectrum of the image in order to increase the digital resolution of the resulting image for that portion of the spectrum of interest.

Sigma-delta analog-to-digital converter

Abstract: A sigma-delta analog-to-digital (A/D) converter comprising an input terminal, an adder, an integrator, a comparator and a flip flop circuit connected in series, with an output signal of the flip flop circuit being provided at an output terminal, and being fed back to the adder through a digital-to-analog (D/A) converter, so that the A/D converter provides a pulse density signal corresponding to a given input signal, wherein the comparator output is isolated from the input terminal of the flip flop circuit, and the output of the flip flop circuit is isolated from the D/A converter input terminal thereby achieving reduction of current consumption. The invention is useful in two wire vortex flowmeters, for example.

Pixel-correlated, digital X-ray imaging system

Abstract: A portable, self-contained, electronic radioscopic imaging system uses a pulsed X-ray source, a remote X-ray sensor, and a self-contained, display and controller unit to produce, store, and/or display digital radioscopic images of an object under investigation An X-ray image sensor configured to spatially sense X-ray radiation pulses includes a pixel clock generator, an integrating CCD camera imager operating in a progressive scan mode providing a discrete pixel readout cycle of sensed X-ray radiation pulses, a sample and hold circuit for sampling the discrete pixel readout responsive to the pixel clock, and an analog to digital converter for digitizing each pixel as the discrete pixel readout is sampled A digital video transmission system controller board controls the X-ray source for acquiring digitized samples from the X-ray image sensor The digital video transmission system has a buffer memory for storing digitized pixels received from the analog to digital converter, and is further provided with a serial interface driver for transmitting the digitized pixels An image processor receives the digitized pixels transmitted by the serial interface driver of the controller for generating a radioscopic image from the digitized pixels

Smart CMOS focal plane arrays: a Si CMOS detector array and sigma-delta analog-to-digital converter imaging system

Abstract: This paper evaluates the potential for the real-time utilization of high frame rate image sequences using a fully parallel readout system. Multiple readout architectures for high frame rate imaging are compared. The application domain for a fully parallel readout system is identified, and the design for a fully parallel, monolithically integrated smart CMOS focal plane array is presented. This focal plane image processing chip, with an 8/spl times/8 array of Si CMOS detectors each of which have a dedicated on-chip current input first-order sigma-delta analog-to-digital converter front end, has been fabricated, and test results for uniformity and linearity are presented.

Multistage analog-to-digital converter employing dither

Abstract: There is disclosed, a converter for converting an input signal from one form to another. The converter includes a slicing circuit adapted to slice a signal into levels. The slicing circuit includes at least one threshold for establishing slicing levels. Dither is employed to vary at least one slicing level in the slicing circuit.

Floating-point analog-to-digital converter

Abstract: A floating-point ADC (FP-ADC) has been proposed for the purpose of achieving a wide dynamic range without demanding a high resolution, when the high resolution is merely for covering the signal dynamic range rather than the quantization accuracy. In an FP-ADC, the dynamic range and resolution can be designed independently. Unlike the known logarithmic amplifier solution, it directly gives a linear digital output. It can work with a small input range imposed by a low voltage supply as its virtual input range is greatly expanded. The principle, key circuitry, achievable performance and sensitivities to mismatches are addressed in this paper. Simulation results indicate that this approach is capable of achieving up to a 16 bit dynamic range with an 8-10 bit effective resolution at a sampling rate of 40 MS/s in submicron CMOS.

Analog-to-digital converter

Abstract: PROBLEM TO BE SOLVED: To provide an analog-to-digital converter which always performs correction and has an excellent S/N even when there are variation and change in analog element constants because of a temperature characteristic, etc. SOLUTION: This device takes the difference between data Y' which is got from output data Y of an A/D modulator 100 that is oversampled through a lowpass filter(LPF) 108 that eliminates out of band noise and output data YD of a delaying device 109 which is delayed only by processing time of the LPF 108. There, a correction value setting device 112 outputs the value of an optimum correction coefficient K to minimize a difference signal, i.e., the level of out of band quantization noise.

Analog to digital converter

Abstract: An analog to digital converter comprises a differential input portion that receives an input voltage and a reference voltage and has a first and second output terminals, a positive feedback portion connected to said first and second output terminals, a buffer if CMOSFETs connected at its input to the first output terminal, a second buffer connected at its input to the second output terminal, and a comparison circuit including a first switching portion connected between the first and second output terminals for connecting and disconnecting the first and second output terminals in response to a comparison clock signal. The comparison circuit is connected at its output to the first or second buffer. The input voltage and the reference voltage are compared when said switching portion changes from the connecting condition to the disconnecting condition in response to the comparison clock signal.

Clocking technique for reducing sampling noise in an analog-to-digital converter

Abstract: A method and apparatus are disclosed for improving the operation of an analog-to-digital converter (“ADC”). A separate “clean” oscillator clock is to be used in combination with a “noisy” ADC clock being regulated by a phase-locked-loop (PLL) circuit. The “noisy” ADC clock drives the digital control logic and also turns on the sample signal for the purpose of sampling. The second clock, which has a substantially fixed (i.e., “clean”) frequency is used to generate a short pulse, the leading edge of which turns off the sample signal, thereby providing an improved sampling process with greater resolution. The interaction of the two clocks is controlled with digital logic circuitry.

Enhanced impulse radar system

Abstract: An impulse radar system useful, for instance, for ground penetration provides three dimensional images of targets. The radar system includes an antenna array with an arrangement of elements that is irregular so that the spacing between elements is different, thereby minimizing redundancy of path geometry between the array elements and the target. This feature reduces unwanted array sidelobes. The radar system incorporates circuitry which permits the utilization of each array element as either a transmitter or receiver antenna element. This dual utilization increases the effective number of elements in the antenna array, providing increased gain and system resolution. The radar system receiver utilizes multiple antenna array receiver elements, each of which is connected sequentially, through a solid state switch, to a single analog to digital converter, thereby providing a digitized signal for processing and display. This arrangement requires only a single analog to digital converter, thereby reducing size, cost, and errors due to analog to digital converter non-linearities.

Hearing aid with beam forming properties

Abstract: The invention relates to a hearing aid with beam forming properties, having at least two microphone channels (1a, 1b) for at least two microphones (2a, 2b), said microphone channels comprising each an analog to digital converter (3a, 3b) and having at least one programmable or program controlled signal processor (5), as well as a digital to analog converter, and at least one receiver and a battery for power supply. The invention particularly comprises in each microphone channel (1a, 1b) a sigma-delta-type analog to digital converter (3a, 3b) including a digital low pass filter and a decimator (4) for converting a 1 Bit Stream of a high clock frequency into a digital word sequence of a lower clock frequency. At least one of said at least two microphone channels contains a controllable delay device (6) connected to the input side of the respective digital low pass filter and decimator (4) of said channel, said delay device (6) being controllable by said at least one signal processor (5). Preferably the delay device (6) is integrated into said sigma-delta-ADC (3).

Cellular handset with adjustable analog to digital conversion

Abstract: A cell phone is provided that may be used with multiple radio formats, such as GSM and CDMA. The cell phone includes a receiver that receives radio signals and converts them into electrical signals. An analog to digital converter is connected to the receiver and converts an analog input to a digital output having an adjustable number of bits at an adjustable sampling frequency. A cell phone application specific integrated circuit is connected to the analog to digital converter, which is used to process the digital output to extract encoded telecommunications data in one of the supported radio formats.

Built-in self-test for analog to digital converter

Abstract: An on-chip analog to digital converter (ADC) test circuit comprises a waveform generator for developing a known arbitrary waveform. A switch selectively connects the waveform generator to the ADC in a test mode or an internal analog input to the ADC in an operate mode. In the test mode the ADC develops a known sequence of digital codes. A signature register is connected to an output of the ADC for receiving and compressing the sequence of digital codes during the test mode. The register develops a single compressed signature representative of the entire ADC digital output sequence. The compression method may be used to test ADC monotonicity, linearity, and that there are no missing codes.

Fully differential interpolating comparator bank and method

Abstract: An interpolating comparator bank having first and second differential amplifiers, each having a differential input and a differential output and first, second and third comparator circuits, each having differential inputs. The differential output of the first differential amplifier and second differential amplifier are coupled to the first and second comparator inputs, respectively. The differential outputs of the first and second differential amplifiers are also both coupled to the differential input of the second comparator circuit. In analog to digital converter circuit applications, the first and second comparators function to provide outputs indicative of the magnitude of a differential input voltage relative to first and third differential reference voltages produced, for example, by a resistor network. The second comparator circuit provides an output indicative of the magnitude of the differential input relative to a second differential input voltage which is not produced by the resistor network but which has a magnitude intermediate that of the first and second differential reference voltages.

Demodulator and method for interferometric outputs of increased accuracy

Abstract: An apparatus and method is presented to provide wide dynamic range balanced measurements of the input phase to an interferometer using a phase generated carrier especially useful utilizing time multiplexing to demodulate a series of interferometers with high accuracy. A modulation drive output is provided by the invention and maintained under operation at the optimum amplitude by an internal feedback loop. The resulting highly stable system which is time balanced, can be fabricated from an analog to digital converter, a digital signal processor, and a digital to analog converter making low cost open loop demodulators a reality.

Nonlinear flash analog to digital converter used in an active pixel system

Abstract: A non-uniform resistor (Fig. 6) is used with a flash analog to digital converter (Fig. 4) in order to provide a non-linear digital output. The non-linear digital output is specifically designed to carry out a predetermined correction of the signal.