Showing papers on "Barrier layer published in 2006"

Contact metallization scheme using a barrier layer over a silicide layer

Abstract: Embodiments of the invention generally provide methods of filling contact level features formed in a semiconductor device by depositing a barrier layer over the contact feature and then filing the layer using an PVD, CVD, ALD, electrochemical plating process (ECP) and/or electroless deposition processes. In one embodiment, the barrier layer has a catalytically active surface that will allow the electroless deposition of a metal on the barrier layer. In one aspect, the electrolessly deposited metal is copper or a copper alloy. In one aspect, the contact level feature is filled with a copper alloy by use of an electroless deposition process. In another aspect, a copper alloy is used to from a thin conductive copper layer that is used to subsequently fill features with a copper containing material by use of an ECP, PVD, CVD, and/or ALD deposition process. In one embodiment, a portion of the barrier layer is purposely allowed to react with traces of residual oxide at the silicon junction of the contact level feature to form a low resistance connection.

Method for forming metal wiring structure

Abstract: A method for forming a metal wiring structure includes: (i) providing a multi-layer structure including an exposed wiring layer and an exposed insulating layer in a reaction space; (ii) introducing an —NH2 or >NH terminal at least on an exposed surface of the insulating layer in a reducing atmosphere; (iii) introducing a reducing compound to the reaction space and then purging a reaction space; (iv) introducing a metal halide compound to the reaction space and then purging the reaction space; (v) introducing a gas containing N and H and then purging the reaction space; (vi) repeating steps (iii) to (v) in sequence to produce a metal-containing barrier layer; and (vii) forming a metal film on the metal-containing barrier layer

A Tracer Study of Porous Anodic Alumina

Abstract: The present study employs a tungsten tracer incorporated into the aluminum substrate to investigate the development of porosity in anodic alumina formed in phosphoric acid electrolyte. An unusual inversion of the tracer distribution is revealed as the tracer layer traverses the barrier region. Although initially incorporated into the barrier layer at locations beneath pore bases, associated with the scalloped metal/oxide interface, the tracer at these locations subsequently lags behind that found at the cell walls. The behavior is contrary to expectations of a field-assisted dissolution model of pore development, with usual migration behaviors of film species in the barrier layer. However, the findings are consistent with pore formation due mainly to flow of alumina from the barrier layer toward the cell walls, driven by film growth stresses. Flow of film material can also account for the presence of phosphorus species in the film and the increased thickness of the film relative to that of the oxidized metal. Anodic alumina films are used extensively in protection and functionalization of aluminum alloys, in electronics through aerospace to architecture. The films are usually formed in aqueous electrolytes, with two morphological types recognized that depend upon composition of the electrolyte, pH, current density, voltage, temperature, etc. Fig. 1. 1-4 Barrier films consist of compact, amorphous alumina of uniform thickness, up to a few hundred nanometers. Porous films comprise a thin barrier layer next to the metal and an outer layer of porous alumina, up to tens of m thick. 2,3 The pores are of approximately cylindrical section and extend from the film surface to the barrier layer. The thickness of the barrier layer and the diameter of the pores are related to the forming voltage, with ratios of 1n m V 1 , while the thickness of the porous layer depends primarily upon the anodizing charge for a particular current density. The porosity has often been explained by massively increased dissolution of the alumina at the pore base under the high electric field of the barrier layer. 5 An early suggestion was made of a role of oxide flow in the dissolution process, with flow occurring due to electrostriction stresses, estimated to be of the order 100 MPa and sufficient to deform oxides. 6

Semiconductor device including FinFET having metal gate electrode and fabricating method thereof

Abstract: Provided are a semiconductor device including a FinFET having a metal gate electrode and a fabricating method thereof. The semiconductor device includes: an active area formed in a semiconductor substrate and protruding from a surface of the semiconductor substrate; a fin including first and second protrusions formed of a surface of the active area and parallel with each other based on a central trench formed in the active area and using upper surfaces and sides of the first and second protrusions as a channel area; a gate insulating layer formed on the active area including the fin; a metal gate electrode formed on the gate insulating layer; a gate spacer formed on a sidewall of the metal gate electrode; and a source and a drain formed in the active area beside both sides of the metal gate electrode. Here, the metal gate electrode comprises a barrier layer contacting the gate spacer and the gate insulating layer and a metal layer formed on the barrier layer.

Nanoparticulate encapsulation barrier stack

Abstract: A barrier stack for encapsulating a moisture and/or oxygen sensitive electronic device is provided. The barrier stack comprises a multilayer film having at least one barrier layer having low moisture and/or oxygen permeability, and at least one sealing layer arranged to be in contact with a surface of the barrier layer, wherein the sealing material comprises reactive nanoparticles capable of interacting with moisture and/or oxygen, thereby retarding the permeation of moisture and/or oxygen through defects present in the barrier layer.

Nitride-based transistors and fabrication methods with an etch stop layer

Abstract: A III-Nitride field-effect transistor, specifically a HEMT, comprises a channel layer, a barrier layer on the channel layer, an etch stop layer on the cap layer, a dielectric layer on the etch stop layer, a gate recess that extends to the barrier layer, and a gate contact in the gate recess. The etch stop layer may reduce damage associated with forming the recessed gate by not exposing the barrier layer to dry etching. The etch stop layer in the recess is removed and the remaining etch stop layer serves as a passivation layer.

Magnetoresistive structure having a novel specular and barrier layer combination

Abstract: A method and system for providing a magnetoresistive structure is disclosed. The magnetoresistive structure includes a pinned layer, a nonmagnetic spacer layer, a free layer, a specular layer, a barrier layer, and a capping layer. The spacer layer resides between the pinned layer and the free layer. The free layer is electrically conductive and resides between the specular layer and the nonmagnetic spacer layer. The specular layer is adjacent to the free layer and includes at least one of titanium oxide, yttrium oxide, hafnium oxide, magnesium oxide, aluminum oxide, nickel oxide, iron oxide, zirconium oxide, niobium oxide, and tantalum oxide. The barrier layer resides between the specular layer and the capping layer. The barrier layer is nonmagnetic and includes a first material. The capping layer includes a second material different from the first material.

Low emissivity coating with low solar heat gain coefficient, enhanced chemical and mechanical properties and method of making the same

Abstract: The invention provides low-emissivity stacks being characterized by a low solar heat gain coefficient (SHGC), enhanced aesthetics, mechanical and chemical durability, and a tolerance for tempering or heat strengthening. The invention moreover provides low-emissivity coatings comprising, in order outward from the substrate a first dielectric layer; a first nucleation layer; a first Ag layer; a first barrier layer; a second dielectric layer; a second nucleation layer; a second Ag layer; a second barrier layer; a third dielectric layer; and optionally, a topcoat layer, and methods for depositing such coatings on substrates.

Deposition of an intermediate catalytic layer on a barrier layer for copper metallization

Abstract: In one embodiment, a method for depositing a conductive material on a substrate is provided which includes exposing a substrate containing a barrier layer to a volatile reducing precursor to form a reducing layer during a soak process, exposing the reducing layer to a catalytic-metal precursor to deposit a catalytic metal-containing layer on the barrier layer, and depositing a conductive layer (e.g., copper) on the catalytic metal-containing layer. The volatile reducing precursor may include phosphine, diborane, silane, a plasma thereof, or a combination thereof and be exposed to the substrate for a time period within a range from about 1 second to about 30 seconds during the soak process. The catalytic metal-containing layer may contain ruthenium, cobalt, rhodium, iridium, nickel, palladium, platinum, silver, or copper. In one example, the catalytic metal-containing layer is deposited by a vapor deposition process utilizing ruthenium tetroxide formed by an in situ process.

Achievement of 4.51% conversion efficiency using ZnO recombination barrier layer in TiO2 based dye-sensitized solar cells

Abstract: The authors report the use of chemically deposited ZnO recombination barrier layer for improved efficiency of TiO2 based dye-sensitized solar cells. The ZnO layers of different thicknesses were deposited on spin coated porous TiO2. The presence of ZnO over TiO2 was confirmed by x-ray diffraction, electron dispersive x-ray analysis, and supported by x-ray photoelectron spectroscopy, proved inherent energy barrier between the porous TiO2 electrode and lithium iodide electrolyte. They found that TiO2 based dye-sensitized solar cell with 30nm ZnO layer thickness showed 4.51% efficiency due to the formation of efficient recombination barrier at electrode/electrolyte interface. Further increase in ZnO barrier thickness may leak the electrons injected from the dye due to its low electron effective mass of 0.2me.

Catalytically enhanced atomic layer deposition process

Abstract: A method for carrying out a damascene process to form an interconnect comprises providing a semiconductor substrate having a trench etched into a dielectric layer, wherein the trench includes a barrier layer and an adhesion layer, depositing a copper seed layer onto the adhesion layer using an ALD process, depositing an iodine catalyst layer onto the copper seed layer using an ALD process, and depositing a copper layer onto the copper seed layer using an ALD process. The iodine catalyst layer causes the copper layer to fill the trench by way of a bottom-up fill mechanism. The trench fill is performed using a single ALD process, which minimizes the creation of voids and seams in the final copper interconnect.

Electrochemical Apparatus With Barrier Layer Protected Substrate

Abstract: The present invention relates to apparatus, compositions and methods of fabricating high performance thin-film batteries on metallic substrates, polymeric substrates, or doped or undoped silicon substrates by fabricating an appropriate barrier layer composed, for example, of barrier sublayers between the substrate and the battery part of the present invention thereby separating these two parts chemically during the entire battery fabrication process as well as during any operation and storage of the electrochemical apparatus during its entire lifetime. In a preferred embodiment of the present invention thin-film batteries fabricated onto a thin, flexible stainless steel foil substrate using an appropriate barrier layer that is composed of barrier sublayers have uncompromised electrochemical performance compared to thin-film batteries fabricated onto ceramic substrates when using a 700° C. post-deposition anneal process for a LiCoO 2 positive cathode.

Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack

Abstract: A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.

Slurry for use in polishing semiconductor device conductive structures that include copper and tungsten and polishing methods

Abstract: A method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The method includes use of a polishing pad with a slurry solution in which copper and a material, such as tungsten, of the barrier layer are removed at substantially the same rate. The slurry is formulated so as to oxidize copper and a material of the barrier layer at substantially the same rates. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry. Systems for substantially polishing copper conductive structures and adjacent barrier structures on semiconductor device structures are also disclosed.

Highly reliable copper dual-damascene interconnects with self-formed MnSi/sub x/O/sub y/ barrier Layer

Abstract: Copper (Cu) dual-damascene interconnects with a self-formed MnSi xOy barrier layer were successfully fabricated. Transmission electron microscopy shows that approximately 2-nm thick and continuous MnSixOy layer was formed at the interface of Cu and dielectric SiO2, and that no barrier was formed at the via bottom because no oxygen was at the via bottom during annealing. No leakage-current increase was observed, and electron energy loss analysis shows that no Cu was in SiO2, suggesting that MnSixOy layer has sufficient barrier properties for Cu, and that the concept of self-forming barrier process works in Cu dual-damascene interconnects. Via chain yield of more than 90% and 50% reduction in via resistance were obtained as compared with physical vapor deposited tantalum barrier, because there is no barrier at the via bottom. In addition, no failure in the stress-induced voiding measurement was found even after a 1600-h testing. No failure in electromigration (EM) testing was found, as the electron flow is from the lower level interconnects through via up to upper level interconnects even after 1000-h testing. At least, four times EM lifetime improvement was obtained in the case of electron flow from upper level interconnect through via down to lower level interconnects. Significant EM lifetime improvement is due to no flux divergence site at the via bottom, resulting from there being no bottom barrier at the via

Deposition methods for barrier and tungsten materials

Abstract: Embodiments are provided for a method to deposit barrier and tungsten materials on a substrate. In one embodiment, a method provides forming a barrier layer on a substrate and exposing the substrate to a silane gas to form a thin silicon-containing layer on the barrier layer during a soak process. The method further provides depositing a tungsten nucleation layer over the barrier layer and the thin silicon-containing layer during an atomic layer deposition process and depositing a tungsten bulk layer on the tungsten nucleation layer during a chemical vapor deposition process. In some examples, the barrier layer contains metallic cobalt and cobalt silicide, or metallic nickel and nickel silicide. In other examples, the barrier layer contains metallic titanium and titanium nitride, or metallic tantalum and tantalum nitride.

Nitride-based semiconductor device and method of manufacturing the same

Abstract: The nitride-based semiconductor device includes a carrier traveling layer 1 composed of non-doped Al x Ga 1-x N (0≦X<1); a barrier layer 2 formed on the carrier traveling layer 1 and composed of non-doped or n-type Al Y Ga 1-Y N (0

Binary group iii-nitride based high electron mobility transistors and methods of fabricating same

Abstract: Aluminum free high electron mobility transistors (HEMTs) and methods of fabricating aluminum free HEMTs are provided In some embodiments, the aluminum free HEMTs include an aluminum free Group III-nitride barrier layer, an aluminum free Group III-nitride channel layer on the barrier layer and an aluminum free Group III-nitride cap layer on the channel layer

System and method for manufacturing thick and thin film devices using a donee layer cleaved from a crystalline donor

Abstract: Various embodiments of fabricated crystalline-based structures for the electronics, optoelectronics and optics industries are disclosed. Each of these structures is created in part by cleaving a donee layer from a crystalline donor, such as a micaceous/lamellar mass comprising a plurality of lamelliform sheets separable from each other along relatively weak cleavage planes. Once cleaved, one or more of these lamelliform sheets become the donee layer. The donee layer may be used for a variety of purposes, including a crystalline layer for supporting heteroepitaxial growth of one or more semiconductor layers thereon, an insulating layer, a barrier layer, a planarizing layer and a platform for creating useful structures, among others.

Reduced dark current photodetector

Abstract: A photo-detector comprising: a photo absorbing layer comprising an n-doped semiconductor exhibiting a valence band energy level; a barrier layer, a first side of the barrier layer adjacent a first side of the photo absorbing layer, the barrier layer exhibiting a valence band energy level substantially equal to the valence band energy level of the doped semiconductor of the photo absorbing layer; and a contact area comprising a doped semiconductor, the contact area being adjacent a second side of the barrier layer opposing the first side, the barrier layer exhibiting a thickness and a conductance band gap sufficient to prevent tunneling of majority carriers from the photo absorbing layer to the contact area and block the flow of thermalized majority carriers from the photo absorbing layer to the contact area. Alternatively, a p-doped semiconductor is utilized, and conductance band energy levels of the barrier and photo absorbing layers are equalized.

A study on the self-sealing process of anodic films on aluminum by EIS

Abstract: The electrochemical behaviors of anodized aluminum in neutral NaCl and Na2SO4 solutions were studied using electrochemical impedance spectroscopy (EIS). The results reveal that there is a self-sealing process for unsealed anodic film in neutral NaCl and Na2SO4 solutions. The resistance of the porous layer (Rp) and the capacitance of the barrier layer (CPEb) increase and the capacitance of the porous layer (CPEp) decreases with immersion time in the initial stage. Corrosion resistance provided by the anodic film is improved by the self-sealing process of the porous layer. However, chloride ions have an opposite effect. The improving effect of the self-sealing process on film resistance is decreased with the increase of chloride concentration of the solution.

Solar assembly with a multi-ply barrier layer and individually encapsulated solar cells or solar cell strings

Abstract: Methods and devices are provided for improved environmental protection for photovoltaic devices and assemblies. In one embodiment, a photovoltaic device module is provided comprising of a multi-ply module encapsulant, a bottom module layer, and a plurality of solar cells. The multi-ply module encapsulant includes one or more discrete layers comprising of at least a first module layer and at least a second module layer. The plurality of solar cells may be sandwiched between the multi-ply module encapsulant and the bottom module layer. At least one of the cells has a protective layer that provides a level of moisture resistance equal to or higher than any of the layers above the cells. The protective layer is typically above the solar cell and light passes through the multi-ply module encapsulant and the protective layer to reach the solar cell.

Plastic Substrates for Flexible Displays

Abstract: New flexible fibrous glass-reinforced plastic (FRP) substrates for flat panel displays were developed. Optimizing the composition of the FRP by adjusting the difference in refractive index between a matrix resin and a glass fiber enabled the coexistence of a high transparency and a low coefficient of thermal expansion (CTE). An excellent smooth surface morphology was confirmed by the formulation of a coating resin. The stability of moisture impermeability depended on the surface smoothness and adhesion between a barrier layer and the coating layer. The moisture permeation rates of barrier substrates were below detection limits (<0.01 g m-2 day-1) on standard measurement equipment.