Showing papers on "Binary number published in 1972"

Effects of finite register length in digital filtering and the fast Fourier transform

Abstract: When digital signal processing operations are implemented on a computer or with special-purpose hardware, errors and constraints due to finite word length are unavoidable. The main categories of finite register length effects are errors due to A/D conversion, errors due to roundoffs in the arithmetic, constraints on signal levels imposed by the need to prevent overflow, and quantization of system coefficients. The effects of finite register length on implementations of linear recursive difference equation digital filters, and the fast Fourier transform (FFT), are discussed in some detail. For these algorithms, the differing quantization effects of fixed point, floating point, and block floating point arithmetic are examined and compared. The paper is intended primarily as a tutorial review of a subject which has received considerable attention over the past few years. The groundwork is set through a discussion of the relationship between the binary representation of numbers and truncation or rounding, and a formulation of a statistical model for arithmetic roundoff. The analyses presented here are intended to illustrate techniques of working with particular models. Results of previous work are discussed and summarized when appropriate. Some examples are presented to indicate how the results developed for simple digital filters and the FFT can be applied to the analysis of more complicated systems which use these algorithms as building blocks.

A Simple Algorithm for Merging Two Disjoint Linearly Ordered Sets

Abstract: In this paper we present a new algorithm for merging two linearly ordered sets which requires substantially fewer comparisons than the commonly used tape merge or binary insertion algorithms. Bounds on the difference between the number of comparisons required by this algorithm and the information theory lower bounds are derived. Results from a computer implementation of the new algorithm are given and compared with a similar implementation of the tape merge algorithm.

A class of finite binary sequences with alternate auto-correlation values equal to zero (Corresp.)

Abstract: An algorithm is presented for the generation of finite binary sequences having an odd number of terms of value + 1 or -1, whose autocorrelation values are zero for odd shifts.

Finiteness Theorems for Binary Forms with Given Discriminant

Abstract: 1. Classical invariant theory is concerned with the action of linear groups on spaces of algebraic forms and the algebraic invariants under such actions; in this paper we are concerned with one of the simplest of such spaces, the space of binary forms of given degree, and one of the simplest invariants, the discriminant of the form. We prove in particular that if Do is a given integer then there are only finitely many GL2(Z)-orbits of binary forms / of given degree n with discriminant D(f) = Do. Before we state our main theorems, we establish our notation and recall some standard definitions. First, suppose that f(x, y) = £?-o aix ~y is a binary form of degree n; if f(x,y) factors as H^=i{j~Pjy)> the discriminant of/ is

Communication system using binary to multi-level and multi-level to binary coded pulse conversion

Abstract: A communication system in which binary coded pulses are translated into multi-level pulses before being transmitted through a communication circuit, at the receiving end of which they are reconverted into binary coded pulses. The binary pulses are grouped into words of n bits, to each of which a (n+1)th-bit of constant value is added. The (n+1) bit words are subdivided into k partial words each having q bits, with (n+1) equal to the product kq. Each one of the partial words is translated into a multi-level pulse of one or the other polarity according to the algebraic sign of the sum of the positive and negative amplitudes of the previously transmitted multi-level pulses. A method for the insertion of synchronization words is described. At the receiving end of the system, the (n+1)th-bit in each group of k partial words is used for controlling the correct restitution of the original binary coded word, by eliminating the ambiguity which otherwise could result from the fact that different multilevel pulses may correspond to identical binary coded partial words, according to their position in the sequence of these words.

A Suggestion for a High-Speed Parallel Binary Divider

Abstract: A family of four procedures to compute the inverse 1/X of a given binary number X normalized between 0.5 and 1 is described. The quotient is obtained in redundant binary form, i.e., in a base 2 code in which digits can assume any positive or negative integer value. All methods here described can be implemented by combinatorial networks; the dividers realized in this way are very fast because all carry propagations take place at the same time.

System for compression of digital data

Abstract: A system for compressing or compacting data that is representative of scanned images. Involved are predictive coding of two level pictorial data, followed by run-length coding characterized by an infinite overflow capability. The predictive stage utilizes an nth-order exhaustive, causal predictor which looks at adjacent points of previous lines and preceding points of present lines to predict what color (black or white) the predictive is. If the prediction is in error, a binary one is transmitted. Alternatively, if the prediction is correct, a binary zero is transmitted. The run-length coding is adapted to code the run-lengths of binary zero between binary one errors using a dual-base counting system, where p represents one base (the number of low order subword states) and n represents a second base (the number of high order subword states) with a subword length, L, of log2 (p + n) bits. Mutually exclusive states in this run-length counting system provide an automatic comma for separating variable-length words (groups of subwords). A significant advantage of this type of run-length number system is that it provides a practical run-length encoding technique with the flexibility of variable-length overflow. The overall data compacting system also achieves a relatively high compression ratio for line drawings and other related type printed matter.

Spectra and Efficiency of Binary Codes Without DC

Abstract: In digital transmission of binary (+1,-1) signals it is desirable that the stream of pulses which constitutes the signal have no dc, that is, that the power spectrum go to zero at zero frequency. It is desirable that, for a given efficiency or entropy, the spectrum rise slowly with increasing frequency. We have obtained the spectrum for selected blocks with equal numbers of plus ones and minus ones. For a given efficiency, this is better than the spectrum obtained by Rice, using the Monte Carlo method, for block encoding using polarity pulses. An algorithm given by Schalwijk should allow simple encoding into selected blocks.

Iterative binary divider utilizing multiples of the divisor

Abstract: A high speed divider is provided for a digital computer for generating a predetermined number of partial quotient bits per iteration by initially using a decode table implemented by a logic network to examine a predetermined number of high order bits of the divisor and another predetermined number of high order bits of the dividend, on the first iteration, and on successive iterations, of the partial remainder. The decode table is generated using the principle that for a given range of the divisor and dividend, as established by fixing the high order digits thereof, a limited range of possible partial quotients exists. The number of difference networks required to form partial remainders is limited to the number of decoded possible values for the partial quotient to be generated. A number of trial possible partial remainders are generated by the difference networks using the multiples of the divisor equal to the decoded possible partial quotient values. A second decode table, implemented by a logic network, determines, from the multiples of the divisor gated to the difference networks, and the results determined therein, which has produced the new partial remainder for the next iteration. The bits of the partial quotient are determined by a selector which examines the multiples of the divisor gated to the difference networks and the network from which the new partial remainder was derived. The process of iteration continues until the entire quotient is generated.

Information coding system

Abstract: A multiple coding system in which a large number of different types of remote sensing units may be monitored by a single station, each sensing unit being identified by its unique code signal. The code signal is produced by generating a series of marker pulses in which only a predetermined combination of the pulses are followed by a code pulse. The monitoring station interprets the predetermined combination as a series of binary numbers identifing the sensing unit, decodes the binary numbers to decimal numbers, and displays the numbers on a panel.

Cellular Array for Extraction of Squares and Square Roots of Binary Numbers

Abstract: A cellular array is described that is capable of extracting either the square or the square root of a binary number. The mode of operation is controlled by a single-mode input line. The array is iterative in its connection pattern and is therefore suitable for large-scale integrated (LSI) implementation. Approximate time-delay expressions are derived, which show that the delays for square or square-root extraction are comparable to the, delay of published array networks.

Two-bit binary divider

Abstract: Method and apparatus for performing 2-bit, non-restore, lookahead, binary division for a digital processor wherein 2 quotient bits are generated simultaneously during one adder cycle; the cycle length needed to develop these 2 bits being essentially limited to the time needed by the adder to perform subtraction. A multiple of the divisor to be subtracted from four times the remainder (4R - MD) for the succeeding cycle is selected concurrently with the remainder developed as a result of the subtraction. A table and decoder are preferably used to examine the magnitudes of the remainder and the divisor to predict this multiplication factor which may also be developed tentatively into the 2-bit quotient. A correction may then be made to the tentative quotient as a result of the adder operation, the corrected quotient being entered into the quotient register.

Variable threshold digital correlator

Abstract: A digital code word correlator for detecting a unique code word in a serially received data stream. The correlator includes a digital adder tree producing a binary number representing the number of matches between the bits of the received word and the bits of a stored replica of the expected unique word. The binary number is supplied to true and complement variable threshold digital comparators which generate detection signals in response to predetermined numbers of matches.

Ternary Logic in Parallel Multipliers

Abstract: The logic cost and speed of parallel multipliers implemented in both binary and ternary logic is studied. Binary operand lengths of 8 through 32 bits and the corresponding ternary digit range of 6 through 21 are considered. For the particular design technique used, the b i i r y versions are slightly faster where the speed criterion is in terms of the longest logic path from operands to product. Ternary designs show smaller total cost of gates and a major reduction in the number of required inputs, indicating greatly simplified wiring interconnection complexity. (Received June 1971)

An Iterative Array for Multiplication of Signed Binary Numbers

Abstract: A simple method for the implementation of Booth's algorithm for multiplication of signed binary numbers has been presented. It has been shown that for large word lengths, a significant economy has been achieved compared to Majithia and Kitai's method.

Modular arithmetic and logic unit

Abstract: A modular and arithmetic logic unit (ALU) for performing logic functions of AND, OR and exclusive OR and arithmetic functions of binary and decimal subtract/add where decimal subtract/add operates with both zoned decimal and decimal data formats. A pair of registers holds the two operands. The outputs of one register feed complement circuitry and the outputs of the other register together with outputs from the complement circuitry go into a subtractor and into borrow look ahead circuitry. The subtractor feeds the borrow look ahead circuitry and function control logic. The outputs from the borrow look ahead circuitry are sent back into the subtractor and one of the outputs is borrow out. The data outputs are taken from a six correct circuit having inputs from the function control logic. Control signals appropriately control the operation of the complement circuit, subtractor, borrow look ahead circuit, function control logic and the six correct circuit.

Orse code type signals digital means for improving the signal to noise ratio of repetitive m

Abstract: A digitally implemented means for enhancing the reception of repetitive binary code transmission sequences is based on a statistical approach of comparing a sampled level of the incoming code at any instant with that received and stored at the time occurrence of the corresponding point on a previously received code sequence. The sampled levels are applied to logic circuitry which modifies stored samples in a plurality of shift registers subject to certain logical constraints. After a sufficient number of input level samples, a substantially noise free replica of the incoming code circulates in the most significant bit one of the plurality of shift registers each of which stores and circulates a progressively more significant bit of a multi-bit stored binary number. Either the input to, or output from, the most significant bit shift register comprises the system output.

Multiple operand addition and multiplication

Abstract: Traditionally, adders used in small- and medium-sized computers are designed to add two n-bit numbers. There are arithmetic operations which require the addition of a large number of numbers. Multiplication (division) and special function generation are such operations. In large computers, "carry save addition", which adds a group of 3 numbers and reduces their sum to a partial sum of two numbers, has been frequently used to speed up multiplication. One of these two partial sums evaluates the sum modulo 2 of bits in the same binary order; the second partial sum being composed from carries generated but not transferred. These partial sums are regrouped in triplets and enter a "carry look ahead" adder to provide the final sum. The circuit implementation is a cascade connection of full adders, and is referred to in the literature as "adder tree". The operation time is considerably reduced because carries are not transferred, although they are formed.

Electronic device for quintupling a binary-coded decimal number

Abstract: An electronic device for quintupling a binary-coded decimal number in which the several orders of binary digits as well as the powers of ten are transmitted through a single channel and represented serially under the control of a clock pulse.

Digital amplitude modulator

Abstract: An envelope modulator which shapes and combines a number of binary input signals by digital means comprises a compact combinatorial logic network, a digital-to-analog converter and a low-pass filter. The logic network operates on the binary input signals to provide at its output a plurality of binary coded bit streams representing a quantized composite of the input signals with a superimposed desired amplitude shaping. The digital-to-analog converter combines the bit streams from the logic network into a quantized signal and the low-pass filter yields a smooth line signal suitable for transmission over bandlimited channels. The elimination of the reactive components required in conventional analog envelope modulators makes this invention capable of operation over a wide range of baud rates.

Analyzed binary computing

Abstract: A single format for the representation of numbers in a computer is proposed to accommodate both exact and inexact quantities. A consistent set of rules is described for addition, multiplication and division of such quantities, both within their separate types, as well as in combination. Error correlation aside, the propagation of inherent errors is monitored in operations with at least one imprecise input. As a simple application, extension of the Forsythe algorithm for finding the roots of a quadratic equation is discussed.

Magnetic bubble counting circuits

Abstract: A new group of magnetic circuits that can count the number of magnetic bubbles and display them in any binary, ternary, ..., decimal basis is proposed. Feasibility of the concept was demonstrated by successful operation of a binary counter circuit. A design of a decimal counter is given.