Showing papers on "Bipolar junction transistor published in 1972"

D-MOS transistor for microwave applications

Abstract: A new n-channel silicon MOS transistor is described that can be fabricated with channel lengths of less than 1 µ by using a double-diffusion process similar to that used in bipolar transistor fabrication. The dimensional tolerances are not tighter than those used in the processing of conventional MOS transistors. This device (called D-MOST) shows gain in the GHz range and a noise figure comparable to that of microwave transistors. The f max is 10 GHz and the noise figure is 4.0 dB at 1 GHz. A brief theory of the D-MOST is followed by the design considerations for a discrete microwave device. Results from s-parameter measurements in the range of 0.1-2.5 GHz are presented along with graphs showing the gains and the stability factor. A simple equivalent circuit is derived from the measurements. Applications of the D-MOST are described.

GaAsGaAlAs heterojunction transistor for high frequency operation

Abstract: A bipolar transistor structure is proposed having application for either high frequency operation or integration with certain types of light emitting devices. The structure involves liquid phase epitaxially grown layers of GaAs for the collector and base regions, and of Ga1−xAlxAs for the heterojunction emitter. The high frequency potential of this device results primarily from the high electron mobility in GaAs and the ability to heavily dope the base region with slowly diffusing acceptors. The Ga1−xAlxAs emitter region provides a favorable injection efficiency and, because it is etched preferentially relative to GaAs, access to the base layer for making contact. Transistor action with d.c. common emitter current gains of 25 have been thus for observed. Calculations of the high speed capability of this transistor are presented.

Modeling of avalanche effect in integral charge control model

Abstract: A compact model for bipolar transistors (integral charge control model) which includes many high-level effects has recently been developed. This model has been shown to give much more accurate results than the conventional Ebers-Moll model. However, avalanche effects have not been included previously. Here a simple expression is developed for the avalanche current generated in the collector junction of a transistor. Avalanche current calculated from this expression agrees very well with the results of exact numerical calculations, which solve the Poisson equation and continuity equations for a realistic structure. With this simple expression, avalanche effects can be incorporated into the integral charge control model with the addition of three model parameters. Output characteristics have been calculated with such a modified integral charge control model and compare very well with measured results demonstrating the accuracy of the avalanche modeling.

Epitaxial outdiffusion technique for integrated bipolar and field effect transistors

Abstract: An NPN transistor, a P channel and an N channel field effect transistor are formed in the same epitaxial layer on a monolithic semiconductor substrate. Subcollector-like areas of one conductivity type are diffused into selected regions of a semiconductor substrate of the opposite conductivity type. Each subcollector-like area comprises two impurities of the same conductivity type but different concentrations and diffusion rates. An epitaxial layer of the same conductivity type as the substrate is grown over the substrate. One of each pair of subcollector impurities outdiffuses completely through the epitaxial layer during the growth of the epitaxial layer and during subsequent heat treatments to define a plurality of isolated pockets of a conductivity type opposite the conductivity type of the surrounding epitaxial layer and substrate. An NPN bipolar transistor and a P channel field effect transistor subsequently are formed in respective isolated pockets. An N channel field effect transistor is formed in the epitaxial layer between the isolated pockets.

Bipolar transistors and method of manufacture

Abstract: A bipolar transistor is fabricated by a process which involves a two-step base formation and an emitter formed by diffusion or ion implantation. One processing step in forming the base is either a diffusion or ion implantation of impurities which step primarily determines sheet resistivity. The other processing step is an ion implantation which primarily determines doping concentration under the emitter. The resulting composite doping profile has at least one point of inflection and is dominated at the surface region by the impurities introduced by the former step and in the bulk by the impurities introduced by the latter step. The emitter is preferably implanted and then diffused to a depth which locates the emitter-base junction past the portion of the base profile dominated by the impurities determining sheet resistivity.

Modeling of bipolar transistor using integral charge-control model with application to third-order distortion studies

Abstract: A compact bipolar transistor model [integral charge-control model (ICM)] has recently been developed that intrinsically includes many high-level effects (for example, conductivity modulation, base push-out effect, Early effect, and impact ionization). This paper presents a detailed characterization of a high-frequency silicon bipolar transistor using the ICM, with sufficient accuracy to allow calculation of intermodulation distortion. A set of electrical measurements for extracting ICM model parameters is described, and the method of extraction is discussed in detail. Finally, calculated values of second- and third-order distortion produced signals are compared with measured values and are found to be in good agreement, which demonstrates the accuracy of the ICM.

Analog transmission gate

Abstract: A transistor switching network, responding to a logic input, switches current selectively into one of a number of nodes, each node connecting a pair of bipolar transistors coupled differentially in a unity gain amplifier circuit. From a number of analog input signals applied to the differentially connected transistor pairs, only the one coupled to the selected node will produce an output from the voltage follower circuit. Conversely, a single analog input signal may be gated selectively to any one of a number of output terminals.

Discovery of anomalous base regions in transistors

Abstract: The theoretical description of transistors has been impeded by the lack of knowledge of the p‐type impurity distributions. A method is described which accurately gives concentration profiles of the boron p‐type regions in transistors. The technique has been used to establish that the base regions in the fastest bipolar transistors are markedly different than usually assumed.

Cross-coupled thyristor storage cell

Abstract: A symmetrical, cross-coupled, two-thyristor storage cell with 1 µW stand-by power dissipation and 60 nsec switching time is described. When integrated in silicon planar technology each thyristor consists of a vertical npn transistor and a lateral pnp transistor.

Double-clamped schottky transistor logic gate circuit

Abstract: A double-clamped Schottky transistor logic gate circuit which includes a totem pole output with Schottky clamp transistors with the pull-down transistor supplying a stable low output level and the pull-up transistor provides a high stable output level voltage by use of a negative feedback arrangement which includes level shifting Schottky diodes and a second Schottky clamp transistor to control the current to the pull-up transistor. An output gating arrangement utilizing Schottky diodes provides reduced capacitances and chip area by placing the cathode of the diode in the same isolated integrated semiconductor regions as the collector of the pull-down transistor. In addition, temperature compensation is provided and noise immunity is improved by integrating a voltage regulator into the same integrated circuit.

Circuit for re-generating a current

Abstract: Integrated circuit for measuring the short-circuit current of a photodiode, which circuit uses the combination of an npn current mirror and a multi-collector lateral pnp transistor the base of which is controlled via a current-amplifying npn transistor.

On the wide-range bias dependence of transistor d.c. and small-signal current gain factors.

Abstract: Critical reappraisal of the bias dependence of the dc and small-signal ac current gain factors of planar bipolar transistors over a wide range of currents. This is based on a straightforward consideration of the three basic components of the dc base current arising due to emitter-to-base injected minority carrier transport, base-to-emitter carrier injection, and emitter-base surface depletion layer recombination effects. Experimental results on representative n-p-n and p-n-p silicon devices are given which support most of the analytical findings.

Fet interface circuit

Abstract: The specification describes an FET circuit for converting bipolar transistor signal levels to field effect transistor (FET) signal levels and includes a capacitor, a signal FET, a load FET and a feedback FET. The feedback FET is connected as a diode between the output of the circuit and the input to the signal FET biasing the input of the signal FET to a predetermined potential level that is slightly in excess of its threshold voltage drop.

Computer-Aided Determination of the Small-Signal Equivalent Network of a Bipolar Microwave Transistor

Abstract: The actual technology for the production of transistors is now suitable for bipolar transistors in the 10-GHz range. In order to obtain amplifier circuits in this microwave range, the knowledge of the exact equivalent circuit is essential. A computer method for the determination of the equivalent network is given. The final application and accuracy are shown for a particular microwave transistor.

Write suppression in bipolar transistor memory cells

Abstract: A circuit is described to suppress or inhibit the driving of bipolar transistors in a memory cell or cells into saturation when a like instruction is already stored in the storage cell or cells. Suppression is accomplished by comparing the information stored in the storage cell with the information applied to the input of the cell, whereby writing is permitted to proceed if the information is not identical and inhibited such if the information is identical.

Mapping of electrical leakage in transistors by anodic oxidation

Abstract: Recently developed electrochemical methods permit the optical mapping of large and small bipolar transistors in an integrated circuit for electrical leakage before metallization. In one methods the emitters of the leaky transistors are decorated by a deposit of amorphous silicon produced as a result of anodic dissolution of the n+silicon in that region. Other methods depend on the colors of the anodic oxide grown on the emitter and base regions of the leaky transistors. A close relationship has been established between the oxide growth on the emitter and the base regions and the defective electrical characteristics of the transistor.

Transistor switching circuit

Abstract: A bistable transistor switching circuit comprising a bipolar transistor adapted to switch states in response to a base node voltage. The circuit further comprises two negative feedback paths. The first comprises a voltage feedback path in which the potential at the transistor emitter terminal responds to a change in emitter current, and the other feedback path comprises a current feedback path through a non-linear impedance located between collector and base terminals.

Apparatus for controlling the energization of a load

Abstract: A plurality of condition responsive impedances, such as PTC thermistors are each connected to reference impedances to form voltage dividers which form half of a bridge circuit. The voltage divider junctions are coupled through diodes to the base of an NPN transistor in the detector of the bridge circuit, the emitter-collector circuit of the transistor being connected across the gate cathode circuit of a silicon controlled rectifier which is used to control the energization of a serially connected relay coil. In the absence of a predetermined condition, such as excessive temperature in a load, the silicon controlled rectifier is gated on each half cycle thereby allowing current to flow through the relay coil to energize the load. On the occurrence of the predetermined condition, i.e., excessive temperature, the impedance value of the condition responsive impedances change and cause conduction of the transistor which shunts current away from the gate of the silicon controlled rectifier thereby deenergizing the relay coil. Differential between the temperature at which energization and deenergization of the system occurs is provided by a reset impedance with contacts coupled thereacross, the contacts being closed when the relay coil is energized. Bypass diodes are connected across the reset and reference impedances to increase the temperature differential and to effect a longer delay before reenergization.

GaAs vapor-grown bipolar transistors

Abstract: Discussion of an approach for the fabrication of high-temperature GaAs transistors which is centered on the preparation of n-p-n three-layered structures entirely by a vapor-phase growth technique, as described by Tietjen and Amick (1966). The low growth temperature of approximately 750 C is thought to reduce contamination during crystal growth and to contribute to the reasonably high minority-carrier lifetimes obtained for the vapor-grown p-n junctions. The fact that impurity concentrations and layer thicknesses can be precisely controlled for epitaxial layers as thin as 1 micrometer is an important feature of this growth technique.

Semiconductor information storage devices

Abstract: A cell of a monolithic semiconductor memory store comprises a bi-directional bipolar transistor, with a capacitance connected to the collector and, with the bipolar transistor capable of conducting in the reverse direction, the capacitance being charged or not charged to store an information bit in the cell, and switching means, such as a field-effect transistor, which is either switched ON or OFF in accordance with the potential difference across the capacitance, there being associated with the cell reading means arranged to produce an output indicative of whether or not the switching means is conducting.

Pulse stretcher for a receiver of a pneumatic tire low pressure monitoring and warning system

Abstract: An electrical apparatus or pulse stretcher is provided and a pneumatic tire low pressure monitoring and warning system using same wherein such apparatus increases the effective time duration of useable electrical signals supplied thereto to thereby activate an indicator associated therewith The apparatus comprises an NPN transistor having base, collector, and emitter electrodes and a cooperating PNP transistor having base, collector, and emitter electrodes with the PNP transistor having its collector electrode connected directly to the indicator and to the base of the NPN transistor by a positive feedback loop, each useable signal being supplied to the base of the NPN transistor through a rectifying diode and stored in a capacitor connected functionally from base to ground The signal operates to turn the PNP transistor ON and simultaneously supply a voltage through the collector electrode of the PNP transistor to activate the indicator whereby the transistors operate to increase the effective time duration of each useable signal supplied to the NPN transistor

A new dielectric isolation technique for bipolar integrated circuits using thin single-crystal silicon films

Abstract: The fabrication and characteristics of bipolar transistors in thin silicon films formed on insulating substrates by an electrochemical etching process are described, and a new technique for achieving complete dielectric isolation of integrated circuits is discussed.

A new complementary bipolar transistor structure

Abstract: A novel complementary monolithic bipolar transistor structure has been developed. By adding one extra diffusion to the standard monolithic bipolar transistor process, a complementary pair of high current gain and very low saturation resistance n-p-n and p-n-p transistors can be fabricated on the same chip. High sheet resistances are also present in this structure. Novel low-voltage (1.3 V) complementary digital circuits have been fabricated by this new process.

Ultra-stable oscillator with complementary transistors

Abstract: A high frequency oscillator, having both good short and long term stability, is formed by including a piezoelectric crystal in the base circuit of a first bi-polar transistor circuit, the bipolar transistor itself operated below its transitional frequency and having its emitter load chosen so that the input impedance, looking into the base thereof, exhibits a negative resistance in parallel with a capacitive reactance. Combined with this basic circuit is an auxiliary, complementary, second bi-polar transistor circuit of the same form as the first bi-polar transistor circuit, with the piezoelectric crystal being common to both circuits. By this configuration, variations in the input impedance of the first bi-polar transistor, resulting from changes in the transitional frequency due to small changes in quiescent current, are substantially cancelled by opposite variations in the second bi-polar transistor circuit, thereby achieving from the oscillator a signal having its frequency of oscillation stable over long time periods as well as short time periods.

Touch tuning and control circuits

Abstract: An electronic circuit for adjusting the volume and tone of an audio signal is controlled by appropriately bridging contacts included therein with a human finger or other conductive means The length of time that a contact is bridged, or closed, determines the conductive state of a field effect transistor associated therewith One such FET controls the gain of an audio amplifier whereby the amplitude of the audio signal is controlled The conductive state of a second such FET controls the biasing voltage on a junction transistor to control the shunting of the high frequency components of the audio signals The audio output is coupled to varactor tuning means so that a change in the conductive state of an FET changes the frequency to which the varactor tuning means is tuned

Semiconductor device having at least two transistors and method of manufacturing same

Abstract: A monolithic integrated semiconductor device according to the invention comprises a group of bipolar transistors of the same type (n-p-n or p-n-p) of which only a first sub-group is provided in insulated islands, said islands being surrounded by cup-shaped insulation zones, the transistors of a second sub-group having a common collector zone and the semiconductor body of the device comprising a low-ohmic substrate on which a high-ohmic epitaxial layer of the same conductivity type as that of the substrate is provided, said substrate belonging to the low-ohmic part of the common collector zone. The first sub-group comprises at least one transistor. Preferably this first transistor is a self-insulating transistor which is provided in or at least adjoins the commen collector zone of the second subgroup, a cup-shaped insulation zone being used which forms part of the base zone of the first transistor and, with the collector zone of the second sub-group forms a p-n junction surrounding the first transistor.

Modeling the "Early effect" in bipolar transistors using an empirical but effective parameter

Abstract: Previous attempts at modeling the "Early effect" in transistors were not valid over wide ranges of operating conditions. A model parameter is defined here which accounts for the desired effects and has the important attributes of being independent of current, temperature, or other parameters for a given device type. The expressions proposed recently by Logan and by Lindholm and Hamilton for including the Early effect in transistor current gain are shown to be equivalent for all temperatures and currents. A new method is proposed for measuring the empirical parameter V N .

Mathematical Simulation of the Effects of Ionizing Radiation on Semiconductors

Abstract: : The report outlines results of two-dimensional mathematical investigations initiated during the present contract period: the insulated gate field-effect transistor, The Schottky barrier field-effect transistor and the bipolar transistor. In addition, information is presented on the mathematical technique used to solve these semiconductor device problems. A discussion is presented on a newly developed method for numerically solving the two- dimensional ambipolar diffusion equations for holes and electrons in semiconductor material. All numerical computations of this type use under relaxation as a means to attain computational stability; the present discussion outlines the automation of this under relaxation process whereby all device calculations can be performed on a 'hands-off' basis. Another new aspect of this computational method is the adoption of a formulation that provides rapid convergence of the calculated electric current in investigations of semiconductor devices.

A monolithic mos/bipolar integrated circuit structure

Abstract: A monolithic integrated circuit structure comprises a wafer of semiconductor material including a semiconductor substrate having an epitaxial layer of semiconductor material thereon, a first region and a second region both of a first conductivity type extending downward from a first surface of said wafer at least partially into said epitaxial layer, said first region being surrounded on all sides except said first surface by a semiconductor material of said first conductivity type of lower resistivity than the first region itself and said second region being partly surrounded by semiconductor material of said first conductivity type of lower resistivity than said second region itself, a semiconductor device of a first type formed in the first region of semiconductor material and a semiconductor device of a second type formed in the second region of semiconductor material, and a lifetime-reducing impurity located in said second region of semiconductor material whereby the switching speed of the semiconductor device of the second type in said second region is improved without substantially changing the characteristics of the semiconductor device of the first type in said first region. Typically the semiconductor device of the first type comprises an MOS device having source and drain regions and the semiconductor device of the second type comprises a bipolar transistor. The switching speed of the bipolar transistor is changed due to the fact that the second region in which the bipolar transistor is formed is not completely surrounded by the semiconductor material of said first conductivity type of lower resistivity than the second region itself.

The bipolar transistor bucket-brigade shift register

Abstract: An analysis of the bipolar transistor bucket-brigade shift-register operation is presented for comparison to other charge-transfer shift-register schemes. It is shown that incomplete charge transfer, the most important performance limiting effect for the charge-coupled device and the IGFET bucket brigade, is very small under most practical operating conditions for the bipolar transistor bucket brigade. In addition to charge loss due to finite transistor current gain h/SUB fe/ the next most important performance limitation comes from collector-emitter capacitance. It is shown that this collector-emitter capacitance leads to reduced analog time delay on transfer through the register and to signal attenuation effects similar to those resulting from incomplete charge transfer. Using the results of the analysis, experimental data reported by Sangster are discussed and a comparison of the advantages and disadvantages of the bipolar bucket-brigade register with the MOS charge-transfer registers is made.