Showing papers on "Channel length modulation published in 1984"

Lucky-electron model of channel hot-electron injection in MOSFET'S

Abstract: The lucky-electron concept is successfully applied to the modeling of channel hot-electron injection in n-channel MOSFET's, although the result can be interpreted in terms of electron temperature as well. This results in a relatively simple expression that can quantitatively predict channel hot-electron injection current in MOSFET's. The model is compared with measurements on a series of n-channel MOSFET's and good agreement is achieved. In the process, new values for many physical parameters such as hot-electron scattering mean-free-path, impact-ionization energy are determined. Of perhaps even greater practical significance is the quantitative correlation between the gate current and the substrate current that this model suggests.

The effect of high fields on MOS device and circuit performance

Abstract: A simple analytical model for the MOS device characteristics including the effect of high vertical and horizontal fields on channel carrier velocity is presented. Analytical expressions for the drain current, saturation drain voltage, and transconductance are developed. These expressions are used to examine the effect of scaling the channel length, the gate dielectric thickness, and the bias voltage on device characteristics. Experimental results from various geometry MOS devices are used to verify the trends predicted by the model. Using the physical understanding provided by the model, we examine the effect of device geometry scaling on circuit performance. We suggest that for gate capacitance-limited circuits one should reduce the channel length, and for parasitic capacitance-limited circuits one should reduce the gate dielectric thickness to improve circuit performance.

Source-and-drain series resistance of LDD MOSFET's

Abstract: The introduction of n- regions makes an LDD MOSFET behave differently from a conventional MOSFET. The source-and-drain series resistance, which consists of the n+-and-n-regions, shows a strong dependence on the gate bias. Also, the apparent effective length can vary with gate bias. These special features cause the traditional method to determine effective channel length and series resistance inapplicable. In this letter, we propose a method to determine the "intrinsic" channel length and gate-voltage-dependent source-and-drain series resistance of an LDD MOSFET and a modal for the LDD device current at small drain-source voltage.

A parametric short-channel MOS transistor model for subthreshold and strong inversion current

Abstract: A parametric model with short-channel capabilities is presented for MOS transistors. It covers the subthreshold and strong inversion regions with a continuous transition between these regions. The effects included in the model are mobility reduction, carrier velocity saturation, body effect, source-drain resistance, drain-induced barrier lowering, and channel length modulation. The model simulates accurately the current characteristics as well as the transconductance and output conductance characteristics which are important for analog circuit simulation.

Accuracy of an effective channel length/External resistance extraction algorithm for MOSFET's

Abstract: The accuracy of an effective channel length/external resistance extraction algorithm for MOSFET's is assessed. This is accomplished by exercising the algorithm with current-voltage data generated by two-dimensional numerical device simulation; the extracted quantities are directly compared to their known counterparts as they exist in the cross section of the simulated device. Extracted effective channel length is found to be within 0.07 µm of the metallurgical channel length in both the conventional and LDD MOSFET's studied here. Extracted external resistance is found to be a reasonable first-order estimate of actual device resistance external to the metallurgical channel but is unable to supply proper information regarding the gate bias dependence of this quantity.

A capacitance method to determine channel lengths for conventional and LDD MOSFET's

Abstract: A simple method for determining the channel length and in situ gate-oxide thickness of MOSFETs is described. The method is based on the linear relationship between the intrinsic gate capacitance and effective channel length. Measurements from two gate biases on devices of different channel lengths are sufficient to obtain a full characterization. In contrast to the channel-resistance method, the accuracy of the capacitance method is independent of the source-drain and contact series resistance. It can, therefore, be used for conventional as well as lightly-doped drain (LDD) devices. Channel length and gate-oxide thickness determined by this method are given for conventional and LDD MOSFET's. For conventional MOSFET's, the new method agrees with the traditional effective length measurements to better than 0.1 µm.

An analytical model for the channel electric field in MOSFET's with graded-drain structures

Abstract: A simple analytical model for the lateral channel electric field in the drain region of MOSFET's with graded-drain or lightly doped drain structures is presented. The model's results agree well with two-dimensional simulations of the electric field in the drain region. Due to its simplicity, this model gives a better understanding of the mechanisms involved in reducing the electric field in the lightly doped region. Results show the impact of the length and doping concentration, assumed to be Gaussian, of the lightly doped region on the electric field. Effects of the oxide thickness and junction depth are also accounted for. In each case, there is an optimum doping concentration that minimizes the peak electric field.

A simple method to determine channel widths for conventional and LDD MOSFET's

Abstract: A new method to determine the channel widths and in situ gate-oxide thicknesses of conventional and LDD MOSFET's is described. The method is based on the linear relationship between the intrinsic gate capacitance and effective channel width. Measurements from two gate biases on devices of different channel widths are sufficient to obtain a full characterization. Channel widths and gate-oxide thicknesses determined by this method are given for both types of devices. This method applies to large-size as well as small-size, test devices.

Proposed vertical-type amorphous-silicon field-effect transistors

Abstract: Novel amorphous-silicon field-effect transistors (a-Si FET's) with a vertical channel have been proposed and demonstrated for the first time. The channel length of the new FET's is not limited by the photoetching process and thus can be reduced a great deal. Prototype FET's with a channel length of 1 µm had an on-off current ratio of more than 104and the on-resistance was proportional to the channel length, so far as it was longer than 1 µm.

An analytic and accurate model for the threshold voltage of short channel mosfets in vlsi

Abstract: Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (

Basic parameter measurement and channel broadening effect in the submicrometer MOSFET

Abstract: An improved measurement technique of the basic MOSFET parameters is presented. This method is based on the measured data of two identical devices with different channel lengths. The effect of series resistance and channel length can be separated from the mobility measurement. This is the only method in which it has been proved that mobility can be measured on a short channel device. A new technique of channel length and series resistance is done by the measurement of newly defined quantity, R T K, which is the equivalent channel length that includes the effect of series resistance. Because of the success of this measurement method, a new phenomena, which we call channel broadening effect, was investigated. Its effects on the submicrometer device characteristics were investigated.

An n-channel MOSFET with Schottky source and drain

Abstract: An n-channel MOSFET with Schottky source and drain (SBMOSFET) has been successfully fabricated using tantalum for the Schottky electrodes. For long gatelengths (100 µm), there are no significant differences in the characteristics of these SBMOSFET's compared to those of conventional MOSFET's. A significant current reduction is observed in SBMOSFET's having 10-µm gatelengths, however, due to the barrier between source and channel. In spite of the substantial barrier height (0.7 V) between tantalum and p-silicon, still larger barriers and a reduction in the isolation gap between source and channel are desirable for high-drive-high-speed device operation.

Submicron Channel MOSFET Using Focused Boron Ion Beam Implantation into Silicon

Abstract: A new submicron channel length device, ion beam MOSFET (IB-MOS), is proposed as an effective application of focused-ion-beam implantation into silicon. The effective channel region of this device is formed by the one line scan of a 16 keV, focused B+ ion beam (diameter: 0.2 µm, current density: 50 mA/cm2) in an As+ implanted n- gate region between the source and drain. It is demonstrated by two dimensional device simulation that significant improvements in current gain, drain breakdown voltage and short-channel threshold effect are achieved for IB-MOS devices with 0.8 µm source-drain spacing. A fabricated IB-MOS device verifies the results of the simulation, except for the current gain, because of the high impurity effect in the channel region, which could be improved by choosing appropriate channel implantation conditions.

Short-channel threshold model for buried-channel MOSFET's

Abstract: An analytical closed-form expression for the short-channel threshold voltage of a normally-OFF-type buried-channel MOSFET (BC-MOSFET) was derived. The model is based on the increase in majority-carrier concentration along the channel and the substrate charge sharing property between source-drain and the channel. This model is able to predict the condition under which the magnitude of the threshold voltage can initially increase and then falls off precipitously as the channel length gradually decreases. Good agreement between theory and experiment was obtained with the p-channel BC-MOSFET used in the CMOS circuit.

A Depletion-Mode MOSFET Model for Circuit Simulation

Abstract: A four-terminal model is formulated for the depletion-mode MOSFET using simple charge-voltage relationships. Different regions of operation are taken into account according to the surface conditions such as accumulation, depletion, and inversion. This simple formulation is then modified to account for the second-order effects such as mobility reduction, drift-velocity saturation, and channel length modulation. Simple expressions are used to express the model parameters in terms of device dimensions. A charge-based capacitance model is used to compute transient currents. The depletion-mode model is implemented in the circuit simulation program HP-SPICE and the simulation results are discussed.

Method of simulating a semiconductor MOSFET

Abstract: A method of simulating the voltage-current characteristics of a short channel metal-oxide-semiconductor field effect transistor (MOSFET) by connecting a series of incremental MOSFETs of different threshold voltages. The threshold voltages near the source and the drain are reduced due to charge sharing. The substrate of each reduced threshold voltage incremental MOSFET is connected to its source. The reduction in threshold voltage can be obtained by Schwartz-Christoffel transformation of the depletion layer edges of the charge sharing region. From these threshold voltages one can calculate the incremental channel conductances and the voltage drops.

A new p-channel MOSFET structure with Schottky-clamped source and drain

Abstract: New p-channel Schottky-Clamped MOSFET'S (SCMOSFET'S) whose source and drain junctions are composed of PtSi Schottky diodes shunted with very small p-n diodes are proposed. The proposed transistors can be fabricated either by silicon V-groove etching or by using boron-doped sidewall oxides. The proposed devices take full advantages of the p-channel Schottky MOSFET while eliminating the problems associated with the Schottky source/drain region, such as low breakdown voltages, high leakage current and a significant reduction of drain current. Moreover, SCMOSFET's reduce the latchup sensitivity in CMOS circuits without any significant increase in technological complexity.

Effects of injection resistance on the performance of very-short-channel MOSFET's

Abstract: Injection resistance, the spreading resistance due to current crowding at the source end of an FET channel, can lead to considerable performance reduction in short-channel MOSFET's. A simple technique for determining the magnitude of this resistance by means of measurements in the linear operation region is described. A simple analytical model which incorporates the effects of both velocity saturation and injection resistance is also developed. The method and model are experimentally verified by determination of the effects of injection resistance on MOSFET's with channel lengths from 0.2 to 24.6 µm.

Fast determination of the effective channel length and the gate Oxide thickness in polycrystalline Silicon MOSFET's

Abstract: MOSFET's with variable channel lengths have been fabricated in both mono- and fine-grained polycrystalline silicon. We present a new method based upon a simple CV technique, to measure the effective channel length and gate oxide thickness. The channel-length reduction of the poly-Si MOSFET's was about 7.8 µm from which an effective lateral diffusion coefficient at 1000°C of phosphorus of 5 × 10-13cm2/s was calculated. The electron mobility was in the range of 10-20 cm2/V.s and the threshold voltage was about 17 V. The MOSFET's in mono-Si have been used as a reference. The results of measurements on these devices are in agreement with literature.

A One-Micrometer Channel Length α-Si Thin-Film Field-Effect Transistor

Abstract: A new method of fabricating short channel α-Si TFTs has been developed. One-micrometer channel length α-Si thin-film field effect transistors have been fabricated and tested. Threshold voltages as low as 1.9V and field-effect mobilities as high as 1 cm 2/V-sec are reported. These devices were fabricated by techniques compatible with the production of large area liquid crystal displays.

Nonuniform displacement of MOSFET channel pinchoff

Abstract: The effects of fixed positive oxide charge under the gate on the characteristics of MOSFET devices are well known The combined effects, however, of the oxide charge in the field and of the edge contour and impurity profile on the device characteristics have not been as extensively investigated in the past In this paper we address this problem and show results which give a new insight in the performance of MOSFET devices With the help of two- and three-dimensional numerical solutions of Poisson's equation, it was found that this oxide charge lowers the threshold potential resulting in an increase in conductivity towards the two edges of the channel along the width direction As a consequence, the geometric channel pinchoff locus shifts towards the drain as the channel edge is approached This is in contrast to the conventional assumption of the pinchoff locus being in parallel to the drain The oxide charge and the net impurity profile under the field region adjacent to the channel causes the current density to increase gradually towards the edges of the channel in channel width direction At high power densities, this may lead to drain-induced corner breakdown Further, in the subthreshold region of device operation, the electric field at the corner of the drain junction is increased, leading possibly to corner breakdown

Small-signal MOSFET one-dimensional admittance model

Abstract: A small-signal a.c. admittance ( y -parameter) circuit model is developed by physical analysis of the basic MOSFET structure by using a small signal analysis. The frequency dependent solutions for the derived set of equations for the y -parameters yield results that match experimental data extremely well. The real parts of the y -parameters vary as ω 2 , while the imaginary parts vary linearly. In carrying out the analysis it was necessary to add parasitic elements to the physical MOSFET model as well as include the effects of channel length modulation. The y -parameters are expressed as a function of the MOSFET parameters, parasitic elements, frequency and bias conditions.

Comments on "Structure-enhanced MOSFET degradation due to hot-electron injection"

Abstract: Hsu and Grinolds recently compared channel hot-electron (CHE) stress results of conventional and "extended drain" NMOS FET's. [1]. They observe increasing degradation as the extended drain resistance increases when the drain bias is defined as that which produces a fixed substrate current. A model in which the hot-electron stress induces surface states within the extended drain region is proposed. We argue that the drain bias condition chosen for these measurements does not produce equal numbers of channel hot electrons in all devices as is claimed. Since the ratio of substrate current to source current is a measure of the mean electron energy, we claim that this ratio (and hence the mean electron energy) increases as extended drain resistance increases.

Nonuniform displacement of MOSFET channel pinchoff

Abstract: The combined effects of the fixed-field oxide change and of the edge contour and impurity profile on MOSFET characteristics are considered, and results are presented which give new insight into the performance of MOSFET devices. It was found that this oxide charge lowers the threshold potential, resulting in an increase in conductivity towards and the two edges of the channel along the width direction. As a consequence, the geometric channel pinchoff locus shifts towards the drain as the channel edge is approached. The oxide charge and the net impurity profile under the field region adjacent to the channels causes the current density to increase gradually towards the edges of the channel, in the channel width direction. At high power densities, this may lead to drain-induced corner breakdown. Further, in the subthreshold region, the electric field at the corner of the drain junction is increased, leading possibly to corner breakdown.