Showing papers on "Clock domain crossing published in 2006"

A 90-nm variable frequency clock system for a power-managed itanium architecture processor

Abstract: An Itanium Architecture microprocessor in 90-nm CMOS with 1.7B transistors implements a dynamically-variable-frequency clock system. Variable frequency clocks support a power management scheme which maximizes processor performance within a configured power envelope. Core supply voltage and clock frequency are modulated dynamically in order to remain within the power envelope. The Foxton controller and dynamically-variable clock system reside on die while the variable voltage regulator and power measurement resistors reside off chip. In addition, high-bandwidth frequency adjustment allows the clock period to adapt during on-die supply transients, allowing higher frequency processor operation during transients than possible with a single-frequency clock system.

Gradient clock synchronization

Abstract: We introduce the distributed gradient clock synchronization problem. As in traditional distributed clock synchronization, we consider a network of nodes equipped with hardware clocks with bounded drift. Nodes compute logical clock values based on their hardware clocks and message exchanges, and the goal is to synchronize the nodes' logical clocks as closely as possible, while satisfying certain validity conditions. The new feature of gradient clock synchronization (GCS for short) is to require that the skew between any two nodes' logical clocks be bounded by a nondecreasing function of the uncertainty in message delay (call this the distance) between the two nodes, and other network parameters. That is, we require nearby nodes to be closely synchronized, and allow faraway nodes to be more loosely synchronized. We contrast GCS with traditional clock synchronization, and discuss several practical motivations for GCS, mostly arising in sensor and ad-hoc networks. Our main result is that the worst case clock skew between two nodes at distance d or less from each other is Ω (d+log D/log log D), where D is the diameter1 of the network. This means that clock synchronization is not a local property, in the sense that the clock skew between two nodes depends not only on the distance between the nodes, but also on the size of the network. Our lower bound implies, for example, that the TDMA protocol with a fixed slot granularity will fail as the network grows, even if the maximum degree of each node stays constant.

Dynamic thermal clock skew compensation using tunable delay buffers

Abstract: The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular by increasing the skew of the clock net and/or altering hold/setup constraints, possibly causing the circuit to operate incorrectly. The knowledge of the spatial distribution of temperature can be used to properly design a clock network that is able to compensate such thermal non-uniformities. However, re-design of the clock network is effective only if temperature distribution is stationary, i.e., does not change over time. In this work, we specifically address the problem of dynamically modifying the clock tree in such a way that it can compensate for temporal variations of temperature. This is achieved by exploiting the buffers that are inserted during the clock network generation, by transforming them into tunable delay elements. Temperature-induced delay variations are then compensated by applying the proper tuning to the tunable buffers, which is computed off-line and stored in a tuning table inserted in the design. We propose an algorithm to minimize the number of inserted tunable buffers, as well as their tunable range (which directly relates to complexity). Results show that clock skew is kept within original bounds with minimum area and power penalty. The maximum increase in power is 23.2% with most benchmarks exhibiting less than 5% increase in power.

Adaptive equalization using correlation of edge samples with data patterns

Abstract: An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

A 120-MHz–1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling

Abstract: A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-mum CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 mm2 and has a peak-to-peak jitter of plusmn6.6 ps at 1.3 GHz

All digital spread spectrum clock generator for EMI reduction

Abstract: An effective solution to control electromagnetic interference in computing appliances such as DVD players or home theater systems is to apply modulation on the system clock. The presence of modulation on the clock reduces the radiated power per unit bandwidth. We present the implementation of a spread spectrum clock generator (SSCG) using strictly digital components. A digital delay line (DDLi) controlled by a small digital circuit is used to increase or decrease the delay on a clock and hence create a modulated output. The DDLi total electrical length is no longer than one period of the 27-MHz reference clock as the digital circuit can adjust to the limited length of the line. The circuit can produce up or down spread by modulating the frequency of the reference with a triangular waveform. The measured peak power reduction is greater than 13 dB for a deviation of about 3% and a frequency modulation of 100 kHz. A real-time digital calibration circuit enables a process and temperature independent operation. The circuit occupies 0.06 mm2 in a 0.15-mum CMOS process and consumes 7.1 mW

Synchronous memory read data capture

Abstract: A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up. Another embodiment of the invention is a simple, low latency clock domain crossing circuit based on the DQS latched sample of the counter.

Jitter requirements of the sampling clock in software radio receivers

Abstract: The effective number of bits of an analog-to-digital converter (ADC) is not only limited by the quantization step inaccuracy but also by sampling time uncertainty. According to a commonly used model, the error caused by timing jitter, integrated over the whole bandwidth, should not be bigger than the quantization noise, for a full swing input signals at the maximum input frequency. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. However, for a radio receiver not the total integrated error is relevant, but only the error signal in the channel bandwidth. This paper explores the clock jitter requirements for a software radio application, using a more realistic model and taking into account the power spectrum of both the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter requirements are very similar to reciprocal mixing requirements of superheterodyne receivers.

A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications

Abstract: This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops for wide multiplication range applications. The DFC loop, which uses variable time period to estimate and tune the frequency of the digitally controlled oscillator (DCO), enhances the resolution of frequency detection. The conventional phase-frequency detector (PFD) and programmable divider are replaced with a digital arithmetic comparator and a DCO timing counter. The value in the DCO timing counter is separated into quotient and remainder vectors. A threshold region is set in the remainder vector to reduce the influence of jitter variation in frequency detection. The loop stability can be retained by cascading two DFC loops when the multiplication factor (N) is large. The proposed clock generator achieves a multiplication range from 4 to 13 888 with output peak-to-peak jitter less than 2.8% of clock period. A test chip for the proposed clock generator is fabricated in 0.18-/spl mu/m CMOS process with core area of 0.16 mm/sup 2/. Power consumption is 15 mW @ 378 MHz with 1.8-V supply voltage.

Injection-Locked Clocking: A New GHz Clock Distribution Scheme

Abstract: We propose a new GHz clock distribution scheme, injection-locked clocking (ILC). This new scheme uses injection-locked oscillators as the local clock regenerators. It can achieve better power efficiency and jitter performance than conventional buffered trees with the additional benefit of built-in deskewing. A test chip is implemented in a standard 0.18?m digital CMOS technology. It has four divide-by-2 ILOs at the leaves of a 3-section H-tree, generating 5GHz local clocks from the 10GHz input clock with 17% locking range and no phase noise degradation. Measured jitter of generated clocks is lower than that of the input signal. Two local clocks can be differentially deskewed up to 80ps relative to each other. The test chip consumes only 7.3mW excluding test-port buffers.

Distributed Differential Oscillators for Global Clock Networks

Abstract: This paper presents a distributed differential oscillator global clock network where the clock capacitance is rendered resonant with a set of on-chip spiral inductors. The clock amplitude and clock phase are both uniform across the entire global distribution, making this design scalable and compatible with existing local clocking methodologies. The resonant network, combined with phase averaging of the distributed oscillator, provides high immunity to process-, voltage-, and temperature-variation-induced timing uncertainty. Measurement results from a prototype design implemented in a 0.18-mum CMOS technology show almost an order of magnitude less jitter and power than a traditional tree-driven grid global clock distribution. On-chip measurement circuits are used to characterize the jitter on the test chip, while a simulation model is used to examine skew and higher-order resonances in the resonant clock network

Synchronized audio/video decoding for network devices

Abstract: A method of synchronizing decoders within a network to a server includes receiving a set of timestamps and local clock signals upon receiving the beacon interrupt signal, computing differential timestamp and local clock values based on values of timestamp and local clock signals, respectively, within the sets of timestamp and local clock signals, determining whether the differential local clock value has a predetermined relationship with the differential timestamp value, and transmitting a clock rate adjustment command signal to the decoder when differential local clock value does not have the predetermined relationship with the differential timestamp value. The clock rate adjustment command signal adjusts (he local system time clock of the decoder such that a subsequent differential dock value will have the predetermined relationship with the differential timestamp value. For each decoder within the network, the decoders are substantially synchronized and the decoding delay can be kept below humanly perceptible levels.

Device for controlling on die termination

Abstract: An on die termination (ODT) control device includes a mode register set for generating a clock control signal based on mode set information; a clock control unit for receiving an internal clock signal and a delay locked loop (DLL) clock signal and outputting an intermediate internal clock signal and an intermediate DLL clock signal in response to the clock control signal; and an ODT control unit for controlling an ODT block by receiving an ODT control signal in response to the intermediate internal clock signal and the intermediate DLL clock signal.

Self-stabilizing Byzantine digital clock synchronization

Abstract: We present a scheme that achieves self-stabilizing Byzantine digital clock synchronization assuming a "synchronous" system. This synchronicity is established by the assumption of a common "beat" delivered with a regularity in the order of the network message delay, thus enabling the nodes to execute in lock-step. The system can be subjected to severe transient failures with a permanent presence of Byzantine nodes. Our algorithm guarantees eventually synchronized digital clock counters, i.e. common increasing integer counters associated with each beat. We then show how to achieve regular clock synchronization, progressing at realtime rate and with high granularity, from the synchronized digital clock counters. There is one previous self-stabilizing Byzantine clock synchronization algorithm, which also converges in linear time (relying on an underlying pulse mechanism), but it requires to execute and terminate Byzantine agreement in between consecutive pulses. Such a scheme, although it does not assume a synchronous system, cannot be easily transformed to a synchronous system in which the pulses (beats) are in the order of the message delay time apart. The only other digital clock synchronization algorithm operating in a similar synchronous model converges in expected exponential time. Our algorithm converges (deterministically) in linear time.

Synchronous clock generator including duty cycle correction

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal The second clock signal is out of phase from the first clock signal by 180 degrees

Delay-locked loop and a method of testing a delay-locked loop

Abstract: A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the clock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.

Digital phase detector improving phase detection resolution thereof

Abstract: A digital phase detector has a plurality of first delay elements through which a first clock is delayed, a plurality of second delay elements through which a second clock is delayed, and a plurality of data holding circuits. The data holding circuits latch the first clock successively delayed through the first delay elements and hold a digital value representing a relative phase difference, in accordance with the second clock successively delayed through the second delay elements. Therefore, the phase detection resolution of the digital phase detector can be improved.

Clock synchronization and distribution over an optical Ethernet network

Abstract: A novel clock synchronization mechanism for recovering and distributing a centralized clock source synchronously over asynchronous networks such as optical Ethernet A clock conversion scheme is provided whereby multiple clocks having diverse rates are converted to clock signals all having a common rate One of the converted clocks is chosen and all downstream clock signals is derived from this clock A high quality clock source located anywhere on the network is distributed throughout the network thus turning an asynchronous Ethernet network into a synchronous one Synchronous TDM data streams can then be easily transported over the Ethernet network

DLL circuit and test method thereof

Abstract: A DLL circuit includes a first delay line circuit, a first phase comparison circuit, a control circuit, and a first selecting circuit. The first delay line circuit can change a delay amount and provide a delay to a first clock signal. The first phase comparison circuit can detect a phase difference between the first clock signal and an output signal of the first delay line circuit, and a phase difference between a test clock signal of which frequency is lower than the first clock signal and an output signal of the first delay line circuit or a signal after dividing the output signal. The control circuit controls a delay amount of the first delay line circuit according to the detection result of the first phase comparison circuit. The first selecting circuit selectively inputs one of the output signal of the first delay line circuit or an inverted signal thereof and the first clock signal to the first delay line circuit.

N-domino register with accelerated non-discharge path

Abstract: A P-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal. The pulsed clock signal lags a symmetric clock signal. The domino stage pre-discharges a pre-discharged node low when the symmetric clock signal is high and opens an evaluation window when the pulsed clock signal goes low, and pulls the pre-discharged node high if it evaluates, and keeps the pre-discharged node low if it fails to evaluate. The output stage provides an output signal based on states of the pre-discharged node and a second preliminary output node.

Semiconductor integrated circuit with delay test circuit, and method for testing semiconductor integrated circuit

Abstract: A semiconductor integrated circuit includes an input side flip-flop; a combinational circuit having an input connected with the input side flip-flop; an output side flip-flop connected with an output of the combinational circuit; and a delay test circuit. The delay test circuit generates output clock pulses by removing an optional one from equal to or more than 3 continuing clock pulses of an input clock signal, and supplies the output clock pulse to the input side flip-flop and the output side flip-flop.

Clock and data recovery circuit having wide phase margin

Abstract: A clock and data recovery (CDR) circuit includes a sampler, a CDR loop and a phase interpolator. The sampler samples serial data in response to a recovery clock signal to generate a serial sampling pulse. The CDR loop transforms the serial sampling pulse into parallel data, generates a plurality of phase signals with a first speed based on the parallel data, and generates a phase control signal with a second speed higher than the first speed based on the plurality of phase signals. The phase interpolator generates the recovery clock signal by controlling a phase of a reference clock signal in response to the phase control signal. Therefore, the CDR circuit may recover data and a clock with a relatively high speed.

Passive keyless entry device

Abstract: A passive keyless entry device includes an in-vehicle transceiver and a portable transceiver. The in-vehicle transceiver has a clock signal generating circuit, a control signal generating signal that outputs a binary control signal having positive and negative values, a modulation circuit that forms a pulse modulation signal by modulating the clock signals by the control signal, and a transmission circuit that has half-bridge circuits, a low-frequency antenna being connected to output ends of the half-bridge circuits. The change time of the control signal from the positive value to the negative value is set to be slightly later than the usual change time from the positive value to the negative value. During a period from the usual change time of the control signal from the positive value to the negative value up to the change time slightly later than the usual change time, the clock signals modulated by the control signal are inverted clock signals that are shifted by half wavelength with respect to the usual clock signals.

Clock buffer polarity assignment for power noise reduction

Abstract: Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. Three assignment algorithms are proposed: (1) partitioning, (2) 2-coloring on minimum spanning tree and (3) recursive min-matching. A post-processing of clock buffer sizing is performed to achieve desired clock skew. SPICE based experimental results indicate that our techniques could reduce the average peak current and average delay variations by 44% and 54% respectively.

Delay locked loop circuit

Abstract: A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.

Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache

Abstract: The clock generation and hybrid clock distribution for a dual-core Xeonreg processor with 16MB L3 cache are designed for <11ps global clock skew in a 435mm2 die. The cache and control sections contain 2 primary clock domains and 11 clock spines. A pipelined de-skew logic tolerant to inter-domain clock uncertainties manages the core and cache/control data communication

A predictive synchronizer for periodic clock domains

Abstract: An adaptive predictive clock synchronizer for systems on chip incorporating multiple clock domains is presented. The synchronizer takes advantage of the periodic nature of clocks in order to predict potential conflicts in advance, and to conditionally employ an input sampling delay to avoid such conflicts. The result is conflict-free synchronization with maximal throughput and minimal latency. The adaptive predictive synchronizer adjusts automatically to a wide range of clock frequencies, regardless of whether the transmitter is faster or slower than the receiver. The synchronizer also avoids sampling duplicate data or missing any input. A novel method is presented for formal treatment of synchronizers and metastability. Correct operation of the synchronizer is formally proven and verified.

Local and broadcast clock synchronization in a sensor node

Abstract: Energy constrained wireless sensor networks need to maintain network timing for coordinating event detection and processing, and to enable receiver duty cycling and communications rendezvous, in order to save energy. Motivated by this, we consider synchronization of a slow low-power local oscillator with an occasionally observed fast and highly accurate broadcast clock (such as GPS). Errors are modeled as quantization noise, incurred when comparing the slow and fast clocks. We consider estimation of the offset and skew between the clocks, detection of drift in the local clock, and prediction of the broadcast clock based on the locally observed times.

Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding

Abstract: In a synchronous clock distribution network with negligible skews, digital circuits switch simultaneously on the clock edge; therefore, they generate a lot of substrate noise due to the resulting sharp peaks on the supply current. A solution is to split a large design in different clock regions and introduce intentional clock skews between them, while taking the timing constraints into account. In this paper, the authors present a complete design flow to optimize the clock tree for less substrate-noise generation in large digital systems. It proposes a technique to assign combinatorial cells and flip-flops to the clock regions. It also takes into account the impact of unintentional clock skew such as jitter on the computed skews in order to assure a robust design. During the optimization, it uses compressed supply-current profiles to improve the CPU time. Experimental results show more than a factor-of-2 reduction in substrate-noise generation from large digital circuits of which the skews are optimized

System and method for testing a clock circuit

Abstract: A test circuit determines whether a frequency of an output clock signal of a clock circuit is above an output threshold frequency. An input clock signal of the clock circuit is set to an elevated frequency that is higher than a specified frequency. A first counter counts the number of clock cycles of the input clock signal in a test interval to within a tolerance of the elevated frequency. The tolerance of the elevated frequency is higher than a tolerance of the specified frequency. A second counter counts the number of clock cycles of a feedback clock signal in the test interval. A comparator determines whether the frequency of the output clock signal is above the output threshold frequency based on the number of clock cycles of the input clock signal and the number of clock cycles of the feedback clock signal.