Showing papers on "Clock synchronization published in 2008"

A New Approach for Time Synchronization in Wireless Sensor Networks: Pairwise Broadcast Synchronization

Abstract: This letter proposes an energy-efficient clock synchronization scheme for Wireless Sensor Networks (WSNs) based on a novel time synchronization approach. Within the proposed synchronization approach, a subset of sensor nodes are synchronized by overhearing the timing message exchanges of a pair of sensor nodes. Therefore, a group of sensor nodes can be synchronized without sending any extra messages. This paper brings two main contributions: 1. Development of a novel synchronization approach which can be partially or fully applied for implementation of new synchronization protocols and for improving the performance of existing time synchronization protocols. 2. Design of a time synchronization scheme which significantly reduces the overall network-wide energy consumption without incurring any loss of synchronization accuracy compared to other well-known schemes.

MU-Sync: a time synchronization protocol for underwater mobile networks

Abstract: Although there are numerous time synchronization algorithms recently proposed for terrestrial wireless sensor networks, none of these could be directly applied to underwater acoustic sensor networks. This is because they typically assume that the propagation delay is negligible, which is not the case in underwater. Furthermore, the sensor nodes in underwater tend to have some degree of mobility due to wind or ocean current, which complicates the problem even more by introducing time-varying delay.In this paper, we propose a cluster-based synchronization algorithm for underwater acoustic mobile networks, called "MU-Sync". Our design avoids frequent re-synchronization by estimating both the clock skew and offset. As underwater mobile networks experience both time-varying and long propagation delay, previous works that estimate the clock skew using a single least square error linear regression tend to be inaccurate. In the MU-Sync, the clock skew is estimated by performing the linear regression twice over a set of local time information gathered through message exchanges. The first linear regression enables the cluster head to offset the effect of long and varying propagation delay; the second regression in turn obtains the estimated skew and offset. With the help of MAC-level time stamping, we can further reduce the nondeterministic errors that are commonly encountered by those synchronization algorithms that rely on message exchanges.

On Maximum Likelihood Estimation of Clock Offset and Skew in Networks With Exponential Delays

Abstract: Clock synchronization represents a crucial element in the operation of wireless sensor networks (WSNs). For any general time synchronization protocol involving a two-way message exchange mechanism, e.g., timing synch protocol for sensor networks (TPSN) [see S. Ganeriwal, R. Kumar, and M. B. Srivastava, "Timing Synch Protocol for Sensor Networks," in Proceedings of the First International Conference on Embedded Network Sensor Systems," 2003, pp. 138-149], the maximum likelihood estimate (MLE) for clock offset under the exponential delay model was derived in [D. R. Jeske, ";On the Maximum Likelihood Estimation of Clock Offset," IEEE Transactions on Communications, vol. 53, no. 1, pp. 53-54, January 2005] assuming no clock skew between the nodes. Since all practical clocks are running at different rates with respect to each other, the skew correction becomes important for achieving long term synchronization since it results in the reduction of the number of message exchanges and hence minimization of power consumption. In this paper, the joint MLE of clock offset and skew under the exponential delay model for a two way timing message exchange mechanism and the corresponding algorithms for finding these estimates are presented. Since any time synchronization protocol involves real time message exchanges between the sensor nodes, ML estimates for other synchronization protocols can be derived by employing a similar procedure. In addition, due to the computational complexity of the MLE, a simple, computationally efficient and easy to implement algorithm is presented as an alternative to the ML estimator which particularly suits the low power demanding regime of wireless sensor networks.

Ultra fast quantum key distribution over a 97 km installed telecom fiber with wavelength division multiplexing clock synchronization

Abstract: We demonstrated ultra fast BB84 quantum key distribution (QKD) transmission at 625 MHz clock rate through a 97 km field-installed fiber using practical clock synchronization based on wavelength-division multiplexing (WDM). We succeeded in over-one-hour stable key generation at a high sifted key rate of 2.4 kbps and a low quantum bit error rate (QBER) of 2.9%. The asymptotic secure key rate was estimated to be 0.78–0.82 kbps from the transmission data with the decoy method of average photon numbers 0, 0.15, and 0.4 photons/pulse.

One-Way Delay Measurement: State of the Art

Abstract: Nowadays, the evaluation of performance measurement in computer networks is an important issue. To ensure the quality of service of the network communication, one of the most important network performance parameters is the one-way delay (OWD). For accurate OWD estimation, it is essential to consider some parameters that can influence the measure, such as the operating system and, in particular, the threads, which are concurrent with the measurement application. Moreover, OWD estimation is not an easy task, because it can be affected by synchronization uncertainties. This paper aims to review the different solutions proposed in the scientific literature for OWD measurement. These solutions adopt different methods to guarantee a reasonable clock synchronization based on the Network Time Protocol, the Global Positioning System, and the IEEE 1588 Standard. These different approaches are critically reviewed, showing their advantages and disadvantages.

An Enhanced IEEE 1588 Time Synchronization Algorithm for Asymmetric Communication Link using Block Burst Transmission

Abstract: IEEE 1588 is a standard to synchronize independent clocks running on separate nodes of a distributed measurement and control system. In IP based cellular network, it is considered as a key technology to synchronize base stations. Especially, interests for the low-cost and very-small home cellular base station called the Femtocell is increasing, and it is connected to the cellular core network using an asymmetric communication link such as xDSL. However, the conventional IEEE 1588 synchronization algorithm assumes symmetrical links, and makes errors for asymmetric links for the calculation of the time difference between the master clock (a clock source) and the slave clock (a clock consumer). We propose an enhanced synchronization algorithm to calculate the asymmetric ratio of the communication link, and the proposed algorithm enhances an accuracy of the time synchronization.

ACES: adaptive clock estimation and synchronization using Kalman filtering

Abstract: Clock synchronization across a network is essential for a large number of applications ranging from wired network measurements to data fusion in sensor networks. Earlier techniques are either limited to undesirable accuracy or rely on specific hardware characteristics that may not be available for certain systems. In this work, we examine the clock synchronization problem in resource-constrained networks such as wireless sensor networks where nodes have limited energy and bandwidth, and also lack the high accuracy oscillators or programmable network interfaces some previous protocols depend on. This paper derives a general model for clock offset and skew and demonstrates its applicability. We design efficient algorithms based on this model to achieve high synchronization accuracy given limited resources. These algorithms apply the Kalman filter to track the clock offset and skew, and adaptively adjust the synchronization interval so that the desired error bounds are achieved. We demonstrate the performance advantages of our schemes through extensive simulations obeying real-world constraints.

A Mutual Network Synchronization Method for Wireless Ad Hoc and Sensor Networks

Abstract: Mutual network synchronization is a distributed method in which geographically separated clocks align their times to one another without the need of reference or master clocks. Mutual network synchronization is attractive for wireless ad hoc and sensor networks, because there is no overhead associated with the discovery, management, and tracking of specific nodes with reference clocks. Existing mutual network synchronization methods, however, make use of physical and medium access control layers that are proprietary and not widely available. This paper presents clock sampling mutual network synchronization (CS-MNS). CS-MNS is able to achieve microsecond networkwide synchronization accuracy for single-hop or multiple-hop network topologies in mobile or static wireless ad hoc and sensor networks. Different from existing mutual network synchronization approaches, the timing information is exchanged explicitly by using periodic time stamp packets. These packets can be, for instance, the same beacons used in the IEEE 802.11 or IEEE 802.15.4 standards, which, to the best of our knowledge, makes CS-MNS the first mutual network synchronization method compatible to these popular standards. A CS-MNS node adjusts the time and frequency of its clock recursively in the time domain by multiplying the time of its clock by a factor that is updated with any newly received time stamp. Sufficient stability conditions are derived via the discrete Lyapunov direct method. Additionally, CS-MNS enables several beacon medium access approaches, which are discussed and analyzed. Thorough numerical results are presented, which demonstrate at least one and two orders of magnitude improvement in scalability and accuracy, respectively, relative to the IEEE 802.11 timing synchronization function (TSF). CS-MNS also shows better accuracy than the multihop ad hoc TSF (MATSF) and the automatic self-time-correcting procedure (ASP) methods under similar scenarios. The latter is achieved with less complexity and with fully compatible IEEE 802.11 beacons.

Frequency Accuracy & Stability Dependencies of Crystal Oscillators

Abstract: Quartz crystal based oscillators are used as clock sources in the synchronization and syntonization of distributed systems to a common time or frequency scale. One such system is that of a cellular network in which base station transceivers are operated within a specified time or frequency accuracy with reference to a system reference. The accuracy of the entrainment of the distributed clocks to the reference clock is subject to the design of the servo control system. In the event the servo fails the slave clock accuracy is a function of the local environmental and electrical stimuli applied to the clock. As loss of the servo signal is a practical issue in a real system, this ultimate system entrainment accuracy is dependent on the accuracy with which the free running clocks can be corrected. It is the subject of the current paper to review the fundamental physical properties of crystal oscillators and in so doing determine all significant frequency perturbing stimuli. Identification and quantification of these stimuli in terms of analytical expressions is the first stage in the creation of an accurate clock model suitable for compensation of the clock in the absence of the servo signal from the reference. Thus a fundamental understanding of the parameters affecting the clock drift becomes paramount to determining the overall synchronization accuracy achievable by the system.

Systems and methods for distributing GPS clock to communications devices

Abstract: A method for synchronizing network elements to a global clock derived from the GPS clock acquired by a plurality of base stations. The global clock is distributed to controllers of various networks, and from there to network access devices. The network access devices further distribute the global clock to various wire-line and local wireless networks and from there, to the users served by these networks. The user equipment is enabled with a simple clock discipliner that adjusts the local clock to the global clock, resulting in a reliable synchronization across the converged communication networks.

Clock synchronization using correlation events

Abstract: Two clocks may be synchronized by calculating skew and offset values that may be determined from several correlation events. A correlation event may be the passing of messages in both directions between the two devices. The skew and offset values may be used to determine the time of non-correlated events. The clock synchronization may be performed on a real time basis or may be performed on a post processing basis. One method for calculating the skew and offset may use inequalities within a solution space to refine a solution set with multiple sets of correlation events.

Apparatus and methods for power saving in USB devices

Abstract: Circuits, architectures, systems, methods, algorithms and software for reducing power consumption of a universal serial bus (USB) device. Exemplary circuits and/or systems include a bus clock synchronization module configured to measure a bus clock period, and a power control module. The power control module is generally configured to determine an application power save period, determine a bus power save period based on the application power save period and the bus clock period, send a power save request, and enter a power saving mode of operation in response to a reply to the power save request. The present embodiments advantageously provide for reduced power consumption of a USB device and faster response during periodic states of activity and inactivity.

UW-FLASHR: achieving high channel utilization in a time-based acoustic mac protocol

Abstract: Time-based medium access control (MAC) has potential advantages over FDMA and CDMA approaches in terms of hardware simplicity, energy efficiency, and delay. Unfortunately, the channel utilization of existing TDMA and CSMA acoustic MAC protocols is generally low due to the long propagation delays of acoustic signals. In this work, we argue that several ideas taken from RF protocols, including exclusive channel access, are either unnecessary in acoustic networks or must be redefined. We present and evaluate UW-FLASHR, a time-based MAC protocol which does not require centralized control, tight clock synchronization, or accurate propagation delay estimation. We demonstrate that UW-FLASHR can achieve significantly higher channel utilization than the maximum utilization possible with existing time-based exclusive access MAC protocols, particularly when the ratio of propagation delay to transmission delay is high or data payloads are small.

Fast self-stabilizing byzantine tolerant digital clock synchronization

Abstract: Consider a distributed network in which up to a third of the nodes may be Byzantine, and in which the non-faulty nodes may be subject to transient faults that alter their memory in an arbitrary fashion. Within the context of this model, we are interested in the digital clock synchronization problem; which consists of agreeing on bounded integer counters, and increasing these counters regularly. It has been postulated in the past that synchronization cannot be solved in a Byzantine tolerant and self-stabilizing manner. The first solution to this problem had an expected exponential convergence time. Later, a deterministic solution was published with linear convergence time, which is optimal for deterministic solutions. In the current paper we achieve an expected constant convergence time. We thus obtain the optimal probabilistic solution, both in terms of convergence time and in terms of resilience to Byzantine adversaries.

Limits of synchronization accuracy using hardware support in IEEE 1588

Abstract: Clock synchronization protocols for packet-oriented networks, like IEEE 1588, depend on time stamps drawn from a local clock at distinct points in time. Due to the fact that software-generated time stamps suffer from jitter caused by non-deterministic execution times, many implementations for high precision clock synchronization rely on hardware support. This allows time readings for packets with very low jitter close to the physical layer. Nevertheless, approaches using hardware support have to carefully consider influences on synchronization accuracy when it comes to the range of nanoseconds. Among others, limits come from the update interval, oscillator stability, or hardware clock frequency. This paper enlightens the limits for such implementations based on an analysis of the influences of the main factors for jitter. The conclusions give hints for efficiently optimizing current implementations.

Clock synchronization for a wireless communications system

Abstract: A method of clock synchronization for a wireless communications system includes receiving a radio frequency (RP) signal at a base station and at a network reference server (NRS). The NRS is also coupled to receive a reference clock signal. A clock offset value is then calculated in response to the RF signal received at the base station, the RF signal received at the NRS, and the reference clock signal. A local clock signal at the base station is then synchronized with the reference clock signal in response to the calculated clock offset value.

Light source apparatus and driving apparatus thereof

Abstract: A light source driving apparatus to drive at least one light source module includes a switch unit for coupling in series with an AC power source and the light source module; a clock synchronization unit for coupling to the AC power source and to provide a clock synchronization signal in accordance with an AC voltage of the AC power source; a control unit coupled to receive the clock synchronization signal and to provide to the switch unit an adjusting signal according to a timing of the clock synchronization signal; and a feedback unit coupled to the control unit and to detect a load state of the light source module, the feedback unit configured to provide to the control unit a feedback signal having a value representative of the detected load state of the light source module. The control unit is configured to modulate a pulse width of the adjusting signal according to the feedback signal and a preset brightness value of the light source module, the switch unit responsive to the adjusting signal to open and close to apply the AC voltage to the light source module in accordance with the modulated pulse width.

Method, Apparatus and System for Frequency Synchronization Between Devices Communicating over a Packet Network

Abstract: An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery loop utilizes a frequency error estimator implemented as a maximum-likelihood estimator with slope fitting based on a sequence of arrival timestamps, and a loop filter implemented as a series combination of an adaptive-bandwidth filter and a proportional-integral controller. The clock recovery module may further comprise a discontinuity detector configured to detect a discontinuity in delays of respective timing messages, and a loop controller operative to place the clock recovery loop in a particular state responsive to detection of the discontinuity.

Adaptive clock and equalization control systems and methods for data receivers in communications systems

Abstract: Systems and methods for adaptive clock and equalization control are provided for data receivers, which are based on a “closed loop” sampling clock framework that employs controllable and dynamically adapted time offsets on both local data and amplitude clocks. The controllable clock offsets are dynamically adapted using signal processing methods adapted to achieve optimum sampling of data and amplitude sampling clock signals to accurately detect data bits and optimize system equalization settings, including, decision-feedback equalizer and/or an optional linear equalizer preceding a decision-feedback equalizer.

IEEE 1588 style synchronization over wireless link

Abstract: We present a technique for synchronizing clocks over a wireless link between a pair of resource constrained nodes. A Kalman filter is used as a pre-processor to a PI controller to mitigate the effects of packet-losses and attenuate noise spikes. This Kalman filter directly tracks the skew, which is the rate of change of offset, between a pair of nodes. The PI controller accepts this skew as input and disciplines the clock on the follower node. Experimental results demonstrate the performance of this technique over a single hop. In the future, this technique can be extended to multihop systems and improve determinism in networked embedded systems.

Network system and optical line terminal

Abstract: It is necessary to completely remove overlapping of signals between plural PONs in order to make the PONs coexist. Accordingly, it is required to share or intensively manage bandwidth use conditions over an optical fiber that serves as a common band between plural systems. Therefore, transmission clocks should be synchronized with high accuracy between plural systems. A reference clock is provided from an external device or a representative OLT to the entire systems to perform clock synchronization between plural systems, so that the overall systems are synchronized by synchronizing each OLT with the reference clock. A hierarchical management method is selected that manages ONUs under the control of each OLT by managing band use information arranged for each OLT with respect to an external device or a representative OLT for sharing of bandwidth use conditions between plural systems.

Exploiting manufacturing variations for compensating environment-induced clock drift in time synchronization

Abstract: Time synchronization is an essential service in distributed computing and control systems. It is used to enable tasks such as synchronized data sampling and accurate time-of-flight estimation, which can be used to locate nodes. The deviation in nodes' knowledge of time and inter-node resynchronization rate are affected by three sources of time stamping errors: network wireless communication delays, platform hardware and software delays, and environment-dependent frequency drift characteristics of the clock source. The focus of this work is on the last source of error, the clock source, which becomes a bottleneck when either required time accuracy or available energy budget and bandwidth (and thus feasible resynchronization rate) are too stringent. Traditionally, this has required the use of expensive clock sources (such as temperature compensation using precise sensors and calibration models) that are not cost-effective in low-end wireless sensor nodes. Since the frequency of a crystal is a product of manufacturing and environmental parameters, we describe an approach that exploits the subtle manufacturing variation between a pair of inexpensive oscillators placed in close proximity to algorithmically compensate for the drift produced by the environment. The algorithm effectively uses the oscillators themselves as a sensor that can detect changes in frequency caused by a variety of environmental factors. We analyze the performance of our approach using behavioral models of crystal oscillators in our algorithm simulation. Then we apply the algorithm to an actual temperature dataset collected at the James Wildlife Reserve in Riverside County, California, and test the algorithms on a waveform generator based testbed. The result of our experiments show that the technique can effectively improve the frequency stability of an inexpensive uncompensated crystal 5 times with the potential for even higher gains in future implementations.

Analysis of a clock-recovery technique for circuit emulation services over packet networks

Abstract: One important requirement of circuit emulation services (CES) over packet networks is clock synchronization and timing distribution among the nodes. CES depends on reliable and high-quality timing for operations. In the time division multiplexing (TDM) world, whether plesiochronous digital hierarchy (PDH), synchronous digital hierarchy (SDH) or synchronous optical network (SONET) based, timing and synchronization is inherent in the design of the network. However, when timing critical services such PDH and SDH/SONET are carried over packet network (e.g. IP, Ethernet, etc.), the timing element is lost and has to be carried across the packet network by other means. A well-known and widely implemented technique for clock recovery in CES is one that is based on packet inter-arrival time (sometimes called time difference of arrival) averaging. The technique is very simple to implement but provides good performance only when packet losses and packet delay variation (PDV) are very low and well controlled. This technique has been extensively analysed through simulations but has not been fully characterized analytically with correlated traffic in the literature. In this paper, we provide a full analytical examination of this well-known clock recovery technique. We analyse the effects of correlation of the delay variation in the traffic stream on the quality of the clock recovered by a receiver. We prove analytically that, for a general input process, high correlation of the delay variation produces a large variance of the recovered clock. Copyright © 2007 John Wiley & Sons, Ltd.

IEEE 1588 syntonization and synchronization functions completely realized in hardware

Abstract: The Precision Time Protocol (PTP) is an application layer protocol and therefore destined to be implemented in software. Hardware functions, if present, include a high resolution clock that helps to generate precise timestamps for PTP messages. The presented paper describes an IEEE 1588 clock that realizes syntonization and synchronization functions completely in hardware. It combines a three-port bridge with peer-to-peer Transparent Clock (TC) functionality and an Ordinary Clock (OC), together with other protocol and application specific logic within an FPGA. The aim of such an implementation is to provide a high accuracy and robust system clock that can be driven by a simple crystal oscillator. It can cope with oscillator instabilities caused by environmental effects such as fast temperature changes or accelerations (shock/vibration). It may deliver synchronicity in deeply cascaded topologies.

Internal clock drift estimation in computer clusters

Abstract: Most computers have several high-resolution timing sources, from the programmable interrupt timer to the cycle counter. Yet, even at a precision of one cycle in ten millions, clocks may drift significantly in a single second at a clock frequency of several GHz. When tracing the low-level system events in computer clusters, such as packet sending or reception, each computer system records its own events using an internal clock. In order to properly understand the global system behavior and performance, as reported by the events recorded on each computer, it is important to estimate precisely the clock differences and drift between the different computers in the system. This article studies the clock precision and stability of several computer systems, with different architectures. It also studies the typical network delay characteristics, since time synchronization algorithms rely on the exchange of network packets and are dependent on the symmetry of the delays. A very precise clock, based on the atomic time provided by the GPS satellite network, was used as a reference to measure clock drifts and network delays. The results obtained are of immediate use to all applications which depend on computer clocks or network time synchronization accuracy.

Clock Synchronization with Bounded Global and Local Skew

Abstract: We present a distributed clock synchronization algorithm that guarantees an exponentially improved bound of O(log D) on the clock skew between neighboring nodes in any graph G of diameter D. In light of the lower bound of Omega(log D/ log log D), this result is almost tight. Moreover, the global clock skew between any two nodes, particularly nodes that are not directly connected, is bounded by O(D), which is optimal up to a constant factor. Our algorithm further ensures that the clock values are always within a linear envelope of real time. A better bound on the accuracy with respect to real time cannot be achieved in the absence of an external timer. These results all hold in a general model where both the clock drifts and the message delays may vary arbitrarily within pre-specified bounds.

Detecting wormhole attacks in wireless networks using local neighborhood information

Abstract: Wormhole attacks enable an attacker with limited resources and no cryptographic material to disrupt wireless networks. In a wormhole attack, an attacker records packets (or bits) at one location in the network, tunnels them (possibly selectively) to another location and retransmits them there into the network. In this paper, we present an algorithm for detecting and thus defending against wormhole attacks in wireless multi-hop networks. This algorithm uses only local and neighborhood information without requiring clock synchronization, location information or dedicated hardware. Moreover, the algorithm is independent of wireless communication models. We present simulation results for grid-like topologies and for random topologies and show that the algorithm is able to detect wormhole attacks in all cases whereas the number of false alarms (false detections) decreases rapidly if the network is sufficiently dense.

Type-matching clock tree for zero skew clock gating

Abstract: Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR gates, and buffer gates. If the logic gates at the same level are in different types, which have different timing behaviors, the control of clock skew becomes difficult. Based on that observation, in this paper, we present a novel clock tree design style, called type-matching clock tree, to ensure that the logic gates at the same level are in the same type. We prove that any clock control logic can always be transformed to our type-matching clock tree. Then, based on the idea of type-matching clock tree, we propose a zero skew gated clock tree synthesis algorithm. Compared with the industry- strength gated clock tree synthesis, experimental data show that our approach can significantly reduce the clock skew in every process corner with a small penalty on the clock tree area and the clock tree power consumption.

Method and apparatus for master-salve clock synchronization

Abstract: The invention discloses a method and a device for synchronizing a master clock and a slave clock, the method comprises: sending synchronous request message to the master clock for many times in a simultaneous cycle by the slave clock, recording the corresponding time value, utilizing a median average filtering algorithm to obtain the optimum time migration amount, utilizing the time migration amount to regulate the slave clock, eliminating delay inequality which is caused by stochastic disturbance and burst interference of a network communication channel between the master clock and the slave clock, guaranteeing the stability of slave clock signals, and increasing the synchronous preciseness of the master clock and the slave clock.