Showing papers on "Digital electronics published in 1979"

Controllability/observability analysis of digital circuits

Abstract: The testability of a digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively. This paper presents a method for analyzing digital circuits in terms of six functions which characterize combinational and sequential controllability and observability.

The prospects for ultrahigh-speed VLSI GaAs digital logic

Abstract: Recent advances of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance GaAs digital ICs with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. The authors evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. GaAs IC fabrication and logic circuit approaches is reviewed. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits.

Testing Logic Networks and Designing for Testability

Abstract: VLSI has brought exciting increases in circuit density and performance capability. But it has also aggravated the problem of chip, component and system testing. Here are some approaches to dealing with that problem.

A Programmable Logic Approach for VLSI

Abstract: This paper explores the use of a proposed programmable storage/logic array (SLA) chip as a general purpose universal logic element for digital computers. The SLA is compared to other programmable logic arrays in implementation and utilization, showing how it permits construction of complete digital subsystems on one chip without sacrifice in programmability. When compared with other contending very large-scale integrated technology (VLSI) approaches, such as microprogrammed processors and gate arrays, the SLA offers an attractive combination of cost, performance, and ease of implementation.

Development Of An Optical Parallel Logic Device And A Half-Adder Circuit For Digital Optical Processing

Abstract: An Optical Parallel Logic (OPAL) device which performs Boolean algebraic operations on two binary images has been developed. This device consists of a photoconductor and an electro-optic light modulating material appropriately arranged to bring about an in-teraction between the input signals. Two such OPAL devices have been interconnected to form a half-adder circuit (one of the essential components in the CPU of a futuristic digital optical processor). Operation of an 8 x 8 OPAL device containing CdS (photoconductor) and twisted nematic liquid crystal (electro-optic light modulating material) is reported. A contrast ratio of 20:1 was obtained. A circuit composed of two such devices is shown to perform addition of two 8 x 8 binary images generating SUM and CARRY images.

The evolution of digital electronics towards VLSI

Abstract: Technological trends are extrapolated to the end of this century. Problems of utilizing high levels of integration are noted, and the capabilities of technology are viewed in the perspective of the problems to provide a forecast of the levels of integration that will be found in large computing systems. A physical model and some more speculative system assumptions are used to estimate the performance of the systems. The physical characteristics forecast for the system are summarized.

Gigabit electronics—A review

Abstract: Digital electronics at gigabit-per-second data rates is emerging as a new branch of science and engineering. A particular field of application opens up in advanced radar and sensing systems where large amounts of data have to be dealt with in real time. Analog-to-digital (A/D) converters with microwave sampling rates and multipliers for high-data-yield processing are specifically required subcircuits. In communications, special 1 to 2 Gbit/s systems have been developed, but a further commercial need develops in domestic satellite links and in fiber-optical communications with its potential high bandwidth capabilities. Corresponding gigabit measuring and test instrumentation is required and being implemented. Gigabit circuitry has so far mainly been realized in hybrid-integrated technology. However, the full use of modern technological tools now allows for the fabrication of gigabit monolithic integrated circuits (IC's), with circuits up to 4 Gbit/s implemented. In circuit design, specific problems must be solved which are due to the involved wide bandwidths at microwave spectral frequencies. High packing density is required for low interconnection delay, but power dissipation leads to limitations. Gigabit electronics is based on devices with switching speeds in the range of a few hundred picoseconds and lower. Besides pin diodes and Schottky diodes, transistors are investigated at first. While the Si bi-polar has been improved, it is the GaAs MESFET and the GaAs junction FET which excel in speed, with LSI capabilities. Very recently, a considerable speed improvement was reported for Si n-MOSFET's. Unique properties for gigabit logic are shown by transferred-electron devices. However, the lead with regard to high speed and low power have Josephson junctions of the in-line junction and of the interferometer types. The present phase of rapid gigabit IC development, with expected LSI circuits in the 2 to 5 Gbit/s range and MSI circuits up to 15 Gbit/s, will stimulate further applications.

Logic Design of Multivalued I 2 L Logic Circuits

Abstract: An algebraic system for designing multivalued (four-level) I2L circuits is presented here. It was necessary to develop this system because the use of existing multivalued logic formalisms does not result in efficient I2L circuits. The close relationship between the algebra and the integrated circuits is stressed throughout the paper.

A 1500 gate, random logic, large-scale integrated (LSI) masterslice

Abstract: Describes the development for the bipolar gate array masterslice for custom designed logic. One chip is designed containing an array of standard logic gates which are then interconnected in a custom manner by using the various levels of metal on the chip. One such masterslice contains 1500 logic gates. The authors describe the physical organization of the chip, and the software package used to assist in simulating the logic, wiring the chip, and generating the patterns needed to test that specific logic function. The internal gate is described in detail, and a discussion of some of the design tradeoffs made is included. The peripheral level-shifting circuits used to interface with a T/SUP 2/L environment and an on-chip reference generating circuit are described. The testing philosophy used, and the package within which the chip is placed are discussed. The paper concludes with a description of the bipolar process used to manufacture the chip.

An integrated per-channel PCM encoder based on interpolation

Abstract: Describes a novel technique called interpolation which has been used to integrate a per channel PCM encoder in a standard digital circuit technology. This encoder converts voiceband analog signals to both an oversampled 1-bit code and uniform PCM with /spl mu/-law companding noise. The circuit comprises approximately 550 integrated injection logic gates together with a resistive digital-to-analog converter, a voltage reference, and a simple differential amplifier. The encoder is part of a full PCM codec chip set suitable for a broad range of voiceband telecommunication applications.

Implementing Parallel Counters with Four-Valued Threshold Logic

Abstract: Parallel counters are multiple-input circuits that count the number of their inputs that are in a given state. They are useful in implementing parallel multipliers, digital summers, digital correlators, and in other digital signal processing capacities. In this paper, the implementation of parallel counters with four-valued threshold logic is described and these implementations are compared to their binary full adder network counter equivalents. This logic form was selected because of the increasing importance of implementing state-of-the-art digital signal processing systems in large-scale-integrated (LSI) circuit form. LSI circuit designs are, in general, limited by the number of metal signal and power lines that must be placed upon the chip's surface, not by the number of active and passive devices used. Since each signal variable in four-valued logic may assume four logic states, twice the information carrying capacity as in binary logic, an over 50-percent savings in the total number of signal variables required to implement the parallel counter results. Also, with the circuits we describe here, approximately 50 percent fewer transistors and resistors are necessary for the implementation of four-valued logic parallel counters. These savings are attainable with a modest tradeoff in speed and power.

Digital logic simulation at the gate and functional level

Abstract: Simulation, in several forms, is used extensively in present day circuit design. The various forms of simulation can be categorized in terms of level of detail offered, ranging from circuit level (transistors, capacitors, etc.) to timing level (e.g., MOTIS (1)) to logic gate level (NAND, NOR, etc.) to register transfer level. As with a microscope, increasing the resolution decreases the field of view. This 'law' imposes a constraint on the size of circuit a designer can simulate at any one level of detail, and most simulation programs are rigidly defined to operate at only one level. This leads to obvious problems, for example, when a circuit is mixed analog/digital, although some progress has been made on incorporating circuit level and gate level detail in one program(2). However, digital circuit sizes keep increasing and even now the gate level often offers too much resolution. To keep simulation costs down and to avoid overwhelming the macroscopic features of a circuit with irrelevant data another level of digital logic simulation is required. The various Hardware Description Languages(3) are too far removed from the gate level to be of much use here as they represent a very large, discrete jump from the gate level, when we would prefer a continuum of simulation resolution.

An integrated interpolative PCM decoder

Abstract: Discusses the technique of time averaging interpolation which provides a means for obtaining telephone quality digital-to-analog conversion using conventional digital integrated-circuit processing. Describes a monolithic circuit that decodes the 8-kHz companded PCM commonly used in voiceband communication systems. The circuit, realized in a standard buried collector bipolar technology, contains 300 integrated injection logic (I/SUP 2/L) gates together with a current-driven resistive ladder network. The performance of the decoder exceeds typical toll network objectives.

Analog-to-Digital Conversion Based on a Voltage-to-Frequency Converter

Abstract: In this paper we discuss a method of analog-to-digital conversion based on a voltage-to-frequency converter (VFC). The basic principle of a VFC circuit is given in order to derive the exact relationship between the characteristics of the output pulse train and the input voltage. We illustrate this theoretical analysis with an example of a simple VFC circuit. The VFC output signal has to be transformed in a binary number proportional to the VFC input voltage. This is done by a digital circuit interfacing the VFC and the computer and a simple calculation in the computer. Finally, we discuss some elements influencing the quantization error of the conversion.

MSI High Speed Low Power GaAs ICs Using Schottky Diode FET Logic

Abstract: A new approach to the design and fabrication of planar high speed GaAs integrated circuits is described. Experimental digital circuits of MSI level complexities have been fabricated showing high gate density, low dynamic switching energies and very high switching speeds.

Circuit for test of ultra high speed digital arithmetic units

Abstract: A method is shown for testing ultra high speed digital arithmetic circuitsr even complete digital signal processors which operate at speeds faster than presently available test equipment. With this technique for testing, the operating speed of digital circuits can be increased until failures occur and then quantitative information on failure rates can be measured.

Logic circuit arrangement in the integrated MOS-circuitry technique

Abstract: A multi-stage logic circuit employing integrated MOS-circuit techniques having gates to produce carry signals between stages where the gates which transfer the carry signals are designed as transfer-gates. Specific circuits are shown for full adders, comparators, synchronous binary counters, forwards-backwards synchronous binary counters and forwards-synchronous counting decades.

A 1500-gate random logic LSI masterslice

Abstract: A LSI bipolar random logic masterslice will be discussed. On a square chip 5.6mm on a side are 1496 logic gates, 88 receiver circuits, 64 driver circuits and two reference generators. Featured, too, are 94 I/O signal lines with voltage levels that are T2L compatible.

Josephson junction current-switched logic circuits

Abstract: A review is given of recent Josephson circuits studies, Emphasis is placed on logic designs employing current-switched gates. These rely on a direct summing of the gate bias current with control current inputs to cause switching from the low-resistance state to the high-resistance state. Present designs are simple, compact and relatively tolerant of fabrication variations. At the same time they retain the advantages of high speed and low power inherent in Josephson devices. Use of these so-called Jaws gates in huffle flip-flops is discussed.

Built-In Test for Complex Digital Integrated Circuits

Abstract: A method for testing the logic function of complex digital integrated circuits is presented. The method is based on built-in test. The extra hardware needed is kept minimal by functional conversion of already existing components (e.g. latches). The feasibility of the proposed method is demonstrated by results from both hardware and logic simulation.

Dual-slope integrating analog-to-digital converter with digital self-calibration

Abstract: With dual-slope integrating analog-to-digital (A/D) converters, which are most frequently used for relatively slow speed conversion, any drift in the operational amplifiers is a very critical factor in limiting their performance. A method has been proposed to eliminate the drift problem completely [1]. This short paper describes a similar but different approach to solve the problem. Some of the advantages are: no necessity for manual adjustments, the use of inexpensive amplifiers instead of costly units with no performance degradation for the temperature range limited only by digital circuits. The old method is more adaptable to ratiometric conversion, while the new method is more adaptable to normal dual-slope integrating A/D conversion with a reference voltage of opposite polarity to input signals. As is the case with the basic dual-slope converters, no precision components are required.

Use of memories and programmable logic arrays for asynchronous sequential circuits

Abstract: The design of asynchronous sequential circuits is commonly related to the problem of observing some specific timing constraints to avoid unreliable behaviour. State assignment and hazard-free construction of the combinational circuits for the state transition equations are the most essential topics to investigate. They contribute significantly to the design, particularly in comparison with that of synchronously operated systems. On the other hand, the application of digital circuitry for solving control tasks implies more and more asynchronous interaction between the controller and the controlled unit, and also the use of modern, highly-integrated modules. This paper investigates the possibility of applying arbitrarily chosen, but unique, codes for state assignments, using l.s.i. memories and programmable logic arrays for implementing more complex asynchronous sequential circuits than is possible with discrete or s.s.i/m.s.i. components. A basic model is derived to describe the time properties of such matrix arrays, and design rules are established to decide easily by some simple measurements, if a given module may be used in that application. The results of a broad investigation into available memories and field-programmable logic arrays show that reliable asynchronous sequential circuits may be implemented without having hazard problems and the need for special state-assignment procedures.

Layout and test design of synchronous LSI circuits

Abstract: A design system for customized low-power digital dynamic circuitry will be described. The logic design process uses synchronous logic. The layout has a row organization which permits automatic layout design and automatic generation of accept-reject information.

Circuit Simulation and Timing Verification based on MOS/LSI Mask Information

Abstract: A mask analysis program for MOS/LSI mask layout data has been developed. This program converts all the mask layout data in one chip LSI into the corresponding circuit schema. A partitioning method for the large random logic circuit divides it into small sub-circuits. It is shown that this method takes full advantage of the savings both in computer time and computer storage for the circuit simulation and timing verification of the random logic circuit having more than 500 active devices.

Expandable arithmetic logic unit

Abstract: This relates to an expandable arithmetic logic unit (ALU) capable of performing binary and BCD addition and subtraction and various logic transfer functions in no more than four stages of logic delay from data input to ALU output. Propagate and generate signals (Pi and Gi) are produced in a single stage of delay and are applied to group propagate and generate logic. The group propagate and group generate signals are produced in a second stage of logic delay and are utilized to form carry look-ahead signals in a third stage of logic delay. Additional logic produces the required logic transfer signals (Hi) one logic delay after generation of the individual Pi and Gi terms. The carry look-ahead signals and logic transfer signals are combined to produce the ALU output.

Logic Verification System for Very Large Computers Using LSI's

Abstract: To aid design verification of very large computers using many LSI's, software tools including a logic simulator with capability of 750,000 gates have been developed.

Implantable programmable electromedical device

Abstract: A programmable medical device, e.g. a cardiac pacemaker, utilizes digital circuitry 40 for controlling the provision of cardiac stimulating pulses and analog circuitry42 for providing clocks, an output circuit and heart activity sensing. Digital circuit 40 includes a memory in which may be programmed on a permanent ortemporary basis from an external programmer control information relating to rate, pulse width, pulse amplitude, refractory period, sense amplifier sensitivity and the mode of operation desired. In addition the output can be inhibited or a threshold margin test can be performed in which a reduced energy output pulse is provided to check if heart capture is lost. The pacemaker can operate in a hysteresis mode and provides a high rate limit which can however be exceeded by programming. The pacemaker further includes means for signalling the acceptance of a programming signal and means to reset the program acceptance circuit if extraneous signals are detected as programming signals. The acceptance circuit checks for the receipt of the proper number of signals within a given time, for an access code and correct parity. Timing is by means of a crystal oscillator and a voltage controlled oscillator controls pulse width to obtain energy compensation with varying battery voltage.