Showing papers on "Drain-induced barrier lowering published in 1984"

GaAs short channel lightly doped drain MESFET structure and fabrication

Abstract: Disclosed is a self-aligned GaAs, lightly doped drain metal-semiconductor field effect transistor. In one embodiment, the device consists of a shallow n- active channel region formed on a GaAs substrate, a Schottky gate overlying the n- region and highly doped and deep n+ source and drain regions formed on either side of the gate. In the channel region between the gate edges and the source/drain are positioned n-type source/drain extensions which have an intermediate depth and doping concentration to minimize the device series resistance, suppress short channel effects and permit channel length reduction to submicron levels. In a second embodiment, p-type pockets are provided under the source/drain extensions to better control the device threshold voltage and further reduce the channel length. In terms of the method of fabrication of the first embodiment, starting with a GaAs substrate an n- semiconductor layer is formed in the device active region. Next, a Schottky gate is formed in direct contact with the n- layer. Next, a dielectric layer is deposited and reactive ion etched (RIE), forming gate sidewalls. Then, n-type source/drain extensions are formed followed by repetition of the dielectric layer deposition and RIE to enlarge the gate sidewalls. Finally, source/drain are implanted. To form the second structure a p-type ion implantation is accomplished prior to or after the source/drain extension forming step to form the deep p-type pockets.

Method of manufacturing an insulated-gate field-effect transistor

Abstract: A method of manufacturing an insulated-gate field-effect transistor on a silicon substrate at high density for large scale integration is disclosed. The source and drain regions of the transistor are formed by implanting low density impurity ions into the silicon substrate and then heating the substrate at a temperature in the range of 900° to 1300° C. Thereafter, additional ions are implanted into the source and drain regions, and the substrate is heated at a second temperature of 700° C., or lower, to provide good ohmic contact between metal electrodes and the source and drain regions. In addition, the sheet resistivity of the source and drain regions is small so that high speed operation of the transistor is achieved.

Low temperature tunneling transistor

Abstract: The transistor comprises two electrodes, (source (22) and drain (23), with a semiconductor tunnel channel (21A, 21B) arranged therebetween. A gate (24) for applying control signals is coupled to the channel. The semiconductor channel consists of a plurality of regions differing in their current transfer characteristics: contact regions (21c), connected to the source and drain electrodes, and a tunneling region (21t) arranged between the contact regions. The energy of free carriers in the contact regions differs from the energy of the conduction band or the valence band of the tunneling region which forms a low energy tunnel barrier the height (ΔE) of which can be modified by control signals applied to the gate. The operating temperature of the device is kept sufficiently low to have the tunnel current through the barrier outweigh currents of thermionically excited carriers.

A new technique for characterization of the "End" resistance in modulation-doped FET's

Abstract: We propose a new extended "end" resistance measurement technique to determine the series source and drain resistance of a field-effect transistor. In this method the small-signal "end" resistance, defined as a derivative of the drain-source voltage, with respect to the gate current, is measured as a function of the drain current. The "end" resistance includes the contributions from the source series resistance and from the resistance related to the conducting channel under the gate. As the drain current increases, the drain side of the channel becomes more reverse biased with respect to the gate. This shifts the gate current distribution towards the source, decreasing the channel contribution to the "end" resistance. By extrapolation to infinite drain current the channel contribution can be eliminated and the series resistance of the undepleted source and drain regions can be accurately determined. The technique is applied to a long-gate modulation-doped field-effect transistor and is shown to Yield reasonable values of the series resistances.

An analytic and accurate model for the threshold voltage of short channel mosfets in vlsi

Abstract: Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (

Zero drain overlap and self aligned contact method for MOS devices

Abstract: The invented technique permits the gate length to equal the channel length: source/drain regions are self-aligned and non-overlapping with respect to their gate electrode. The non-overlapping feature, along with other optimized device characteristics, are generally provided by defining a gate electrode over a substrate, forming an implant mask of dielectric, for example, on the sides of the gate electrode, and implanting a source/drain region such that the implant mask shields a portion of the substrate from implantation to provide a gap between a side edge of the gate electrode and the implanted regions. The source/drain region is then heat driven until its side edge is substantially aligned with the edge of the gate electrode. Self-aligned source/drain contacts are also provided using the implant mask to isolate the gate electrode from the contacts and interconnects.

Low voltage hot-electron effects in short channel MOSFETs

Abstract: This work presents experimental evidence of hot electron injection into the gate oxide of submicron-size MOSFETs at applied voltages well below the minimum threshold for a simple physical interpretation in terms of the widely accepted lucky electron model. The results are then explained showing that at low voltages substantial Auger recombination takes place in the critical channel region near the drain and plays the essential role of a further mechanism providing some field-hot electrons with the extra energy needed to surmount the Si-SiO 2 interfacial barrier.

A new approach to the modeling of nonuniformly doped short-channel MOSFET's

Abstract: A new doping transformation procedure for the modeling of arbitrarily doped enhancement-mode MOSFET's is presented. The procedure is based on conservation of charge and electrostatic energy in the depletion region along with the conservation of surface potential and depletion width. The transformation can be extended to short-channel MOSFET's using a charge sharing approximation. Experimental results obtained on n-well CMOS devices with effective channel lengths down to 1.5 µm are used to verify the validity of the models for threshold voltage, drain conductance, and drain current.

Schottky barrier field effect transistors

Abstract: A high-grain MESFET (i.e. a Schottky barrier FET) has a gate electrode present directly on a semiconductor body. A highly doped layer, which forms parts of the channel of the transistor, extends below the gate electrode between the source and drain regions respectively. A highly doped surface region of opposite conductivity type to the highly doped layer is present between the gate electrode and the highly doped layer. This surface region, which is so thin that it is fully depleted in the zero gate bias condition, raises the effective height of the Schottky barrier. The highly doped layer is so thin that it can support without breakdown an electric field greater than the critical field for avalanche breakdown of the semiconductor material for this layer. Thus, the doping concentration of the highly doped layer can be increased so that more charge can be depleted from it. The highly doped surface region extends beyond the gate electrode on the drain side of the semiconductor to reduce the surface electric field. Another layer, which is more lightly doped than the highly doped layer of the same conductivity type, increases the mobility of charge carriers in the channel.

Vertical MOSFET with current monitor utilizing common drain current mirror

Abstract: An improvement in a constant current circuit comprising a metal oxide semi-conductor field effect transistor (MOSFET) integrated circuit (IC) for providing a feedback voltage indicative of current flow as a control parameter for either on-off mode or linear feedback mode. The improvement comprises the usual drain, gate and source terminals with an additional feedback terminal and dual, parallel connected FET's formed into the MOSFET IC and connected in parallel to the drain and gate terminals. One of the FET's is much larger and has a much greater current carrying capability than the second one and the second one is connected serially with a resistor, the juncture of the second field effect transistor and resistor being connected with the feedback terminal to give a voltage indicative of current flow at the drain terminal.

Method of making a high voltage DMOS transistor

Abstract: A process for manufacturing a high voltage DMOS (Deep Diffusion Metal Oxide Semiconductor) transistor includes a first ion implantation and drive-in step to form a P-well in a N-substrate, and a second such step to form a N+ region in this well and a channel between this region and the substrate and under a polysilicon gate which is covered with a silicon nitride layer during the first step. By the presence of the latter layer pitting of the gate is prevented and no leakage paths are formed between source and drain.

Zener referenced threshold detector with hysteresis

Abstract: In reference to a voltage level detector Zener, the voltage at which a switching transistor (Q1) opens is determined by the breakdown voltage of a Zener diode (Z1) coupled between ground and the base of transistor switching means (Q1) in conjunction with the base-emitter voltage of the switching transistor itself. To protect the circuit noise threshold detector at the trigger point, a portion of the collector current of the switching transistor is fed to a second transistor (Q2) which, once opened, reduce the voltage at the base of the switching transistor (Q1).

Method of simulating a semiconductor MOSFET

Abstract: A method of simulating the voltage-current characteristics of a short channel metal-oxide-semiconductor field effect transistor (MOSFET) by connecting a series of incremental MOSFETs of different threshold voltages. The threshold voltages near the source and the drain are reduced due to charge sharing. The substrate of each reduced threshold voltage incremental MOSFET is connected to its source. The reduction in threshold voltage can be obtained by Schwartz-Christoffel transformation of the depletion layer edges of the charge sharing region. From these threshold voltages one can calculate the incremental channel conductances and the voltage drops.

Read only semiconductor memory device with polysilicon drain extensions

Abstract: A semiconductor memory device is formed of a polycrystalline silicon electrode terminal layer, which is formed on a MOS transistor except over the gate region and is connected to the drain region of the MOS transistor, and metal wire layer, which is formed on the MOS transistor except over the gate region and is connected to the electrode terminal layer to transmit output signals. Data is written into the semiconductor memory device by ion implantation of the gate of the MOS transistor after the metal wire layer is formed.

Vertical mos transistor

Abstract: PURPOSE:To enable the decrease in ON-resistance without deteriorating other characteristics, by a method wherein at least part of the drain region is formed out of a Schottky barrier. CONSTITUTION:The titled element consists of a Schottky metal 1, semiconductor substrate 2, channel diffused layers 3, source diffused layers 4, source electrodes 5, and a gate electrode 6. In other words, the drain region is not made N or P but made Schottky junction. Since the Schottky junction gets a small amount of mirror carrier injection and is very high in switching speed, a Schottky junction is used for the drain region of a vertical MOS transistor so as to largely reduce the resistance of the semiconductor substrate region 2 without damaging the characteristics of the MOS transistor.

Modification of most I-V characteristics by self-heating

Abstract: A MOS transistor, when passing drain current, dissipates power in the channel region. This results in a temperature rise within the channel area, which can modify the I-V behaviour of the transistor. In this paper, we have calculated the channel temperature as a result of power dissipated by the device, by solving the heat diffusion equation. The modified I-V behaviour of the MOS transistor due to this channel heating has been predicted and matches experimentally observed phenomena. In particular, the negative dynamic resistance observed in the saturation region of MOS transistors operating at elevated power densities has been explained.

A One-Micrometer Channel Length α-Si Thin-Film Field-Effect Transistor

Abstract: A new method of fabricating short channel α-Si TFTs has been developed. One-micrometer channel length α-Si thin-film field effect transistors have been fabricated and tested. Threshold voltages as low as 1.9V and field-effect mobilities as high as 1 cm 2/V-sec are reported. These devices were fabricated by techniques compatible with the production of large area liquid crystal displays.

Semiconductor device for obtaining an accurate threshold voltage adjustment

Abstract: The invention relates to an integrated MOS circuit comprising a MOS transistor which is connected as a resistor and which, when conducting current, generates a voltage which is supplied to the source/gate of a second field effect device. In order to obtain a suitable current adjustment, the two channel widths are chosen so that due to narrow channel effects, a difference (though small) in threshold voltage is obtained. The invention is of particular interest for CCD input circuits for generating a small offset voltage required for supplying FAT-zero.

Threshold voltage instability of a static RAM under 77-K operation

Abstract: Threshold voltage instability of MOSFETs in an n-MOS static RAM under accelerated operating test conditions at 77 K has been studied. It is found that under high bias operations (supply voltage ≥ 7 V) at 77 K, a threshold voltage shift occurs, due to the presence of negative and positive charges in the gate oxide. The negative charge is caused by trapping the injected electrons in the pre-existing electron traps. The majority of electrons are thermally re-emitted, as the samples are warmed to room temperature. On the other hand, the presence of positive charges is a dominant factor in the threshold voltage shift under these test conditions. A simple quantitative model to explain the mechanism of positive charge generation responsible for the negative threshold-voltage shift is proposed. Some samples show that, from the analysis, the amount of saturated negative shift in threshold voltage can be estimated to be 100 mV at most.

Digital switching circuit having insulated gate field effect transistors for clamping the nonconductive output transistor off

Abstract: In a push-pull switching circuit, whose output transistors are controlled by complementary control signals, one of the gate electrodes which carries a "low" signal is kept just at the threshold voltage of the output transistor to be cut off by means of a transistor substantially identical to the output transistors, the gate electrode and the drain electrode of this transistor being interconnected. The junction of this gate and this drain is connected to the common of two cross-coupled transistors, which are connected by their drains to the gate electrodes of the respective output transistors.

Calculation of the threshold voltage of metal‐oxide‐semiconductor field‐effect transistors with Pearson‐IV channel doping profile

Abstract: In this paper, a general analytical expression for the calculation of threshold voltage of an ion‐implanted n‐channel enhancement‐mode metal‐oxide‐semiconductor field‐effect transistor with a Pearson‐IV channel dopant distribution is presented. Specifically, the threshold voltage in excess of the flat‐band voltage is characterized as an explicit function of the four moments about the mean depth of the dopant distribution, namely, projected range, standard deviation, skewness, and kurtosis. The effects of substrate doping concentration, implant dose, and the body effect on the threshold voltage are also presented.

Comments on "Structure-enhanced MOSFET degradation due to hot-electron injection"

Abstract: Hsu and Grinolds recently compared channel hot-electron (CHE) stress results of conventional and "extended drain" NMOS FET's. [1]. They observe increasing degradation as the extended drain resistance increases when the drain bias is defined as that which produces a fixed substrate current. A model in which the hot-electron stress induces surface states within the extended drain region is proposed. We argue that the drain bias condition chosen for these measurements does not produce equal numbers of channel hot electrons in all devices as is claimed. Since the ratio of substrate current to source current is a measure of the mean electron energy, we claim that this ratio (and hence the mean electron energy) increases as extended drain resistance increases.

Regenerative switching in V-groove metal oxide semiconductor field-effect transistor structure

Abstract: Anomalous regenerative switching has been observed in a power V-groove MOSFET with the drain terminal of the MOSFET at the top surface of the chip. This switching phenomenon is attributed to a rectifying junction formed at the drain terminal due to a thin oxide between the drain metal and the n -type drain diffusion. Because of the regenerative switching, the device characteristic changes from the MOSFET I ( V ) characteristic to a turned-on thyristor characteristic as the gate voltage is increased to a critical voltage. The ON-resistance of the device in the thyristor mode is found to be one-tenth of that in the MOSFET mode. Based on the explanation of the experimental results, an insulated gate controlled thyristor structure with substrate as the cathode is proposed.

D.C. Voltage bias circuit in an integrated circuit

Abstract: In an integrated circuit having an amplifier with its input terminal connected to a signal input terminal, a D.C. voltage bias circuit is provided which includes a D.C. bias voltage generator and a depletion mode MOS transistor connected at its source-drain path between the bias voltage generator and the signal input terminal and coupled at its gate electrode to either its source or its drain thus preventing breakdown of the gate insulating film of the depletion mode MOS transistor resulting from a surge voltage from the signal terminal.

Digital signal switching circuit

Abstract: In a pushpull switching circuit, whose output transistors are controlled by complementary control signals, that one of the gate electrodes which carries a "low" signal is kept just at the threshold voltage of the output transistor to be cut off by means of a transistor (substantially) identical to the output- transistors, the gate electrode and the main electrode (drain) of this transistor being interconnected. The junction (of this gate and this drain) is connected to sources (main electrodes) of two cross-coupled with gate and drain transistors, which are connected by their drain to the gate electrodes of the respective output reansistors.