Showing papers on "Electronic design automation published in 2022"
06 Jun 2022
TL;DR: This paper provides a comprehensive survey of available EDA and CAD tools, methods, processes, and techniques for Integrated Circuits (ICs) that use machine learning algorithms.
Abstract: An increase in demand for semiconductor ICs, recent advancements in machine learning, and the slowing down of Moore's law have all contributed to the increased interest in using Machine Learning (ML) to enhance Electronic Design Automation (EDA) and Computer-Aided Design (CAD) tools and processes. This paper provides a comprehensive survey of available EDA and CAD tools, methods, processes, and techniques for Integrated Circuits (ICs) that use machine learning algorithms. The ML-based EDA/CAD tools are classified based on the IC design steps. They are utilized in Synthesis, Physical Design (Floorplanning, Placement, Clock Tree Synthesis, Routing), IR drop analysis, Static Timing Analysis (STA), Design for Test (DFT), Power Delivery Network analysis, and Sign-off. The current landscape of ML-based VLSI-CAD tools, current trends, and future perspectives of ML in VLSI-CAD are also discussed.
12 citations
TL;DR: In this article , an artificial-intelligence-based design (AI-D) approach is proposed for parameter design of power converters, where simulation tools and batch normalization neural network (BN-NN) are adopted to build data-driven models for the optimization objectives and design constraints.
Abstract: Parameter design is significant in ensuring a satisfactory holistic performance of power converters. Generally, circuit parameter design for power converters consists of two processes: analysis and deduction process and optimization process. The existing approaches for parameter design consist of two types: traditional approach and computer-aided optimization (CAO) approach. In the traditional approaches, heavy human-dependence is required. Even though the emerging CAO approaches automate the optimization process, they still require manual analysis and deduction process. To mitigate human-dependence for the sake of high accuracy and easy implementation, an artificial-intelligence-based design (AI-D) approach is proposed in this article for the parameter design of power converters. In the proposed AI-D approach, to achieve automation in the analysis and deduction process, simulation tools and batch-normalization neural network (BN-NN) are adopted to build data-driven models for the optimization objectives and design constraints. Besides, to achieve automation in the optimization process, genetic algorithm is used to search for optimal design results. The proposed AI-D approach is validated in the circuit parameter design of the synchronous buck converter in the 48 to 12 V accessory-load power supply system in electric vehicle. The design case of an efficiency-optimal synchronous buck converter with constraints in volume, voltage ripple, and current ripple is provided. In the end of this article, feasibility and accuracy of the proposed AI-D approach have been validated by hardware experiments.
12 citations
TL;DR: A comprehensive review of recent advances in the design automation of CFMBs, including CAD techniques for architecture synthesis, volume assignment and sample preparation, testing, fault-tolerant design, and washing are presented.
9 citations
TL;DR: RWRoute as mentioned in this paper is an open source timing-driven router for UltraScale+ devices, which is built on the RapidWright framework and includes the essential and pragmatic features found in commercial FPGA routers that are often missing from open source tools.
Abstract: One of the key obstacles to pervasive deployment of FPGA accelerators in data centers is their cumbersome programming model. Open source tooling is suggested as a way to develop alternative EDA tools to remedy this issue. Open source FPGA CAD tools have traditionally targeted academic hypothetical architectures, making them impractical for commercial devices. Recently, there have been efforts to develop open source back-end tools targeting commercial devices. These tools claim to follow an alternate data-driven approach that allows them to be more adaptable to the domain requirements such as faster compile time. In this paper, we present RWRoute, the first open source timing-driven router for UltraScale+ devices. RWRoute is built on the RapidWright framework and includes the essential and pragmatic features found in commercial FPGA routers that are often missing from open source tools. Another valuable contribution of this work is an open-source lightweight timing model with high fidelity timing approximations. By leveraging a combination of architectural knowledge, repeating patterns, and extensive analysis of Vivado timing reports, we obtain a slightly pessimistic, lumped delay model within 2% average accuracy of Vivado for UltraScale+ devices. Compared to Vivado, RWRoute results in a 4.9× compile time improvement at the expense of 10%
Quality of Results (QoR) loss for 665 synthetic and six real designs. A main benefit of our router is enabling fast partial routing at the back-end of a domain-specific flow. Our initial results indicate that more than 9× compile time improvement is achievable for partial routing. The results of this paper show how such a router can be beneficial for a
low touch flow to reduce dependency on commercial tools.
9 citations
TL;DR: A comprehensive review of recent advances in the design automation of CFMBs, including CAD techniques for architecture synthesis, volume assignment and sample preparation, testing, fault-tolerant design, and washing, is presented in this paper .
7 citations
TL;DR: In this article , the authors present the first open-source dataset called CircuitNet for ML tasks in VLSI CAD, which is used for cross-stage prediction tasks in the design flow to achieve faster design convergence.
Abstract: The electronic design automation (EDA) community has been actively exploring machine learning (ML) for very large-scale integrated computer-aided design (VLSI CAD). Many studies explored learning-based techniques for cross-stage prediction tasks in the design flow to achieve faster design convergence. Although building ML models usually requires a large amount of data, most studies can only generate small internal datasets for validation because of the lack of large public datasets. In this essay, we present the first open-source dataset called CircuitNet for ML tasks in VLSI CAD.
6 citations
13 Apr 2022
TL;DR: A novel discerning ensemble technique for cross-design ML prediction for macro placement based on a large number of designs with different design styles and technology nodes is developed and tested and shows great promise for many ML problems in EDA applications, or even in other areas.
Abstract: Modern very large-scale integration (VLSI) designs typically use a lot of macros (RAM, ROM, IP) that occupy a large portion of the core area. Also, macro placement being an early stage of the physical design flow, followed by standard cell placement, physical synthesis (place-opt), clock tree synthesis and routing, etc., has a big impact on the final quality of result (QoR). There is a need for Electronic Design Automation (EDA) physical design tools to provide predictions for congestion, timing, and power etc., with certainty for different macro placements before running time-consuming flows. However, the diversity of IC designs that commercial EDA tools must support and the limited number of similar designs that can provide training data, make such machine learning (ML) predictions extremely hard. Because of this, ML models usually need to be completely retrained for unseen designs to work properly. However, collecting full flow macro placement ML data is time consuming and impractical. To make things worse, common ML methods, such as regression, support vector machine (SVM), random forest (RF), neural network (NN) in general, lack a good estimation of prediction accuracy or confidence and lack debuggability for cross-design applications. In this paper, we present a novel discerning ensemble technique for cross-design ML prediction for macro placement. We developed our solution based on a large number of designs with different design styles and technology nodes, and tested the solution on 8 leading-edge industry designs and achieved comparable or even better results in a few hours (per design) than manual placement results that take many engineers weeks or even months to achieve. Our method shows great promise for many ML problems in EDA applications, or even in other areas.
5 citations
TL;DR: A comprehensive review of the existing works linking the EDA flow for chip design and Graph Neural Networks is presented, mapping those works to a design pipeline by defining graphs, tasks, and model types and summarizing challenges faced when applying GNNs within the Eda design flow.
Abstract: Driven by Moore’s law, the chip design complexity is steadily increasing. Electronic Design Automation (EDA) has been able to cope with the challenging very large-scale integration process, assuring scalability, reliability, and proper time-to-market. However, EDA approaches are time and resource demanding, and they often do not guarantee optimal solutions. To alleviate these, Machine Learning (ML) has been incorporated into many stages of the design flow, such as in placement and routing. Many solutions employ Euclidean data and ML techniques without considering that many EDA objects are represented naturally as graphs. The trending Graph Neural Networks (GNNs) are an opportunity to solve EDA problems directly using graph structures for circuits, intermediate Register Transfer Levels, and netlists. In this article, we present a comprehensive review of the existing works linking the EDA flow for chip design and GNNs. We map those works to a design pipeline by defining graphs, tasks, and model types. Furthermore, we analyze their practical implications and outcomes. We conclude by summarizing challenges faced when applying GNNs within the EDA design flow.
5 citations
29 Oct 2022
TL;DR: A comprehensive overview of the usage of GNNs in hardware security can be found in this paper , where the authors divide the state-of-the-art GNN-based hardware security systems into four categories: IP piracy detection systems, reverse engineering platforms, and attacks on logic locking.
Abstract: Graph neural networks (GNNs) have attracted increasing attention due to their superior performance in deep learning on graph-structured data. GNNs have succeeded across various domains such as social networks, chemistry, and electronic design automation (EDA). Electronic circuits have a long history of being represented as graphs, and to no surprise, GNNs have demonstrated state-of-the-art performance in solving various EDA tasks. More importantly, GNNs are now employed to address several hardware security problems, such as detecting intellectual property (IP) piracy and hardware Trojans (HTs), to name a few.In this survey, we first provide a comprehensive overview of the usage of GNNs in hardware security and propose the first taxonomy to divide the state-of-the-art GNN-based hardware security systems into four categories: (i) HT detection systems, (ii) IP piracy detection systems, (iii) reverse engineering platforms, and (iv) attacks on logic locking. We summarize the different architectures, graph types, node features, benchmark data sets, and model evaluation of the employed GNNs. Finally, we elaborate on the lessons learned and discuss future directions.
5 citations
17 Jan 2022
TL;DR: A hybrid RL and analytical mixed -size placer is developed and an RL-inspired optimizer for analog circuit sizing is developed, combining the strengths of deep neural networks and reinforcement learning to achieve state-of-the-art black-box optimization results.
Abstract: Reinforcement learning (RL) algorithms have recently seen rapid advancement and adoption in the field of electronic design automation (EDA) in both academia and industry. In this paper, we first give an overview of RL and its applications in EDA. In particular, we discuss three case studies: chip macro placement, analog transistor sizing, and logic synthesis. In collaboration with Google Brain, we develop a hybrid RL and analytical mixed -size placer and achieve better results with less training time on public and proprietary benchmarks. Working with Intel, we develop an RL-inspired optimizer for analog circuit sizing, combining the strengths of deep neural networks and reinforcement learning to achieve state-of-the-art black-box optimization results. We also apply RL to the popular logic synthesis framework ABC and obtain promising results. Through these case studies, we discuss the advantages, disadvantages, opportunities, and challenges of RL in EDA.
3 citations
27 Apr 2022
TL;DR: A reinforcement learning method enhanced by graph learning to automate the analog circuit parameter optimization at the pre-layout stage, i.e., finding device parameters to fulfill desired circuit specifications, breaking the limitations of prior learning methods in designing conventional analog circuits.
Abstract: The design automation of analog circuits is a longstanding challenge. This paper presents a reinforcement learning method enhanced by graph learning to automate the analog circuit parameter optimization at the pre-layout stage, i.e., finding device parameters to fulfill desired circuit specifications. Unlike all prior methods, our approach is inspired by human experts who rely on domain knowledge of analog circuit design (e.g., circuit topology and couplings between circuit specifications) to tackle the problem. By originally incorporating such key domain knowledge into policy training with a multimodal network, the method best learns the complex relations between circuit parameters and design targets, enabling optimal decisions in the optimization process. Experimental results on exemplary circuits show it achieves human-level design accuracy (~99%) with 1.5× efficiency of existing best-performing methods. Our method also shows better generalization ability to unseen specifications and optimality in circuit performance optimization. Moreover, it applies to design radio-frequency circuits on emerging semiconductor technologies, breaking the limitations of prior learning methods in designing conventional analog circuits.
12 Jun 2022
TL;DR: A toolbox in Matlab/Octave that contains all native functions required by analog designers to capture an entire design strategy in an executable script capable of executing an analog circuit design fully automatically.
Abstract: This paper presents a toolbox in Matlab/Octave for procedural design of analog integrated circuits. The toolbox contains all native functions required by analog designers (namely, schematic-generation, simulation setup and execution, integrated look-up tables and functions for design space exploration) to capture an entire design strategy in an executable script. This script - which we call an Expert Design Plan (EDP) - is capable of executing an analog circuit design fully automatically. The toolbox is integrated in an existing design flow. A bandgap reference voltage circuit is designed with this tool in less than 15 min.
30 Oct 2022
TL;DR: In this paper , the authors use Graph Neural Networks (GNNs) to estimate the timing behavior of chip components at different stages of the design process, such as register transfer level (RTL), to increase the quality of the results and lower the flow iterations.
Abstract: In the Electronic Design Automation (EDA) flow, signoff checks, such as timing analysis, are performed only after physical synthesis. Encountered timing violations cause re-iterations of the design flow. Hence, timing estimations at initial design stages, such as Register Transfer Level (RTL), would increase the quality of the results and lower the flow iterations. Machine learning has been used to estimate the timing behavior of chip components. However, existing solutions map EDA objects to Euclidean data without considering that EDA objects are represented naturally as graphs. Recent advances in Graph Neural Networks (GNNs) motivate the mapping from EDA objects to graphs for design metric prediction tasks at different stages. This paper maps RTL designs to directed, featured graphs with multidimensional node and edge features. These are the input to GNNs for estimating component delays and slews. An in-house hardware generation framework and open-source EDA tools for ASIC synthesis are employed for collecting training data. Experiments over unseen circuits show that GNN-based models are promising for timing estimation, even when the features come from early RTL implementations. Based on estimated delays, critical areas of the design can be detected, and proper RTL micro-architectures can be chosen without running long design iterations.
TL;DR: In this paper, the authors present an approach for separating controller design and their software implementations in isolated design spaces using respective COTS design tools, which can lead to long debugging a controller.
Abstract: Controller design and their software implementations are usually done in isolated design spaces using respective COTS design tools. However, this separation of concerns can lead to long debugging a...
29 Oct 2022
TL;DR: The ICCAD 2022 CAD Contest Problem C calls for an effective design space exploration algorithm to solve the problem as mentioned in this paper , which is formulated as a contest problem and provides benchmark suites, contest benchmark platforms, etc.
Abstract: It is vital to select microarchitectures to achieve good trade-offs between performance, power, and area in the chip development cycle. Combining high-level hardware description languages and optimization of electronic design automation tools empowers microarchitecture exploration at the circuit level. Due to the extremely large design space and high runtime cost to evaluate a microarchitecture, ICCAD 2022 CAD Contest Problem C calls for an effective design space exploration algorithm to solve the problem. We formulate the research topic as a contest problem and provide benchmark suites, contest benchmark platforms, etc., for all contestants to innovate and estimate their algorithms.
01 Jan 2022
TL;DR: In this article , two approaches for an automated interpretation of surface-skeletons for CAD-reconstruction are presented, one based on decomposing the input in analytical, the other in polygonal surfaces.
Abstract: Geometry reconstruction from 3D topology optimization results to Computer Aided Design (CAD) is challenging, especially for automation and non-beam-like geometry. While the optimized model has polygonal format, product development with CAD requires analytical surfaces in Boundary Representation (BRep). In this paper, we present two approaches for an automated interpretation of surface-skeletons for CAD-reconstruction. This includes the question, when to convert the skeleton’s polygonal to analytical surfaces and how to conceptually incorporate CAD features. One approach is based on decomposing the input in analytical, the other in polygonal surfaces. Both approaches work with specific skeleton-features and lead to a CAD-model with BRep-reconstruction. Exemplary results are presented.
TL;DR: In this article , a hybrid Josephson transmission line and passive transmission line routing framework is proposed to improve the overall performance of a single flux quantum (SFQ) circuit, where an efficient routing algorithm is applied during the layout design to perform accurate timing adjustment for fixing hold violations and optimizing critical paths.
Abstract: The single flux quantum (SFQ) logic family is a novel digital logic as it provides ultrafast and energy-efficient circuits. For large-scale SFQ circuit design, specialized electronic design automation (EDA) tools are required due to the differences in logic type, timing constraints, and circuit architecture, in contrast to the Complementary metal–oxide–semiconductor (CMOS) logic. In order to improve the overall performance of an SFQ circuit, an efficient routing algorithm should be applied during the layout design to perform accurate timing adjustment for fixing hold violations and optimizing critical paths. Thus, a hybrid Josephson transmission line and passive transmission line routing framework is proposed. It consists of four main modules and an exploration of the potential timing performance based on the given layout placement. The proposed routing tool is demonstrated on seven testbench circuits. The obtained results demonstrate that the operating frequency is greatly improved, and all the hold violations are eliminated for each circuit.
13 Apr 2022
TL;DR: A review of deterministic methods for sizing, structural synthesis and layout synthesis of analog circuits, which have been developed over the past decades, and a summary of the underlying mindset of analog design automation.
Abstract: While the majority of research in design automation for analog circuits has been relying on statistical solution approaches, deterministic approaches are an attractive alternative. This paper gives a few examples of deterministic methods for sizing, structural synthesis and layout synthesis of analog circuits, which have been developed over the past decades. It starts from the so-called characteristic boundary curve for interactive parameter optimization, and ends at recent approaches for structural synthesis of operational amplifiers based on functional block composition. A deterministic approach to analog placement and to yield optimization will also be described. The central role of structural analysis of circuit netlists in these approaches will be explained. A summary of the underlying mindset of analog design automation and an outlook on future opportunities for deterministic sizing and layout synthesis concludes the paper.
TL;DR: This paper will find out the key technologies in the EDA field through 3D sand table clustering algorithm, and analyze a series of patent data of monopoly three companies in order to help local EDA enterprises perceive the technology status and development trend of the international Eda field.
Abstract: Currently, Electronics Design Automation (EDA) software tools are highly monopolized internationally. In China, EDA suffers from the pain of “stuck neck”. This paper will find out the key technologies in the EDA field through 3D sand table clustering algorithm, and analyze a series of patent data of monopoly three companies (Synopsys, Cadence, Mentor Graphic), in order to help local EDA enterprises perceive the technology status and development trend of the international EDA field.
TL;DR: In this article , the authors proposed a novel model based on graph convolutional networks to predict the total runtime of a given stage on different configurations, achieving a prediction accuracy of 87%.
Abstract: Design space exploration in logic synthesis and parameter tuning in physical design require a massive amount of compute resources in order to meet tapeout schedules. To address this need, cloud computing provides semiconductor and electronics companies with instant access to scalable compute resources. However, deploying electronic design automation (EDA) jobs on the cloud requires EDA teams to deeply understand the characteristics of their jobs in cloud environments. Unfortunately, there has been little to no public information on these characteristics. Thus, in this article, we first formulate the problem of moving EDA jobs to the cloud. To address the problem, we characterize the performance of four EDA main applications, namely: 1) synthesis; 2) placement; 3) routing; and 4) static timing analysis. We show that different EDA jobs require different compute configurations in order to achieve the best performance. Using observations from our characterization, we propose a novel model based on graph convolutional networks to predict the total runtime of a given stage on different configurations. Our model achieves a prediction accuracy of 87%. Furthermore, we present a new formulation for optimizing cloud deployments in order to reduce costs while meeting deadline constraints. We present a pseudopolynomial optimal solution using a multichoice knapsack mapping that reduces deployment costs by 35.29%, with minimal overhead to the total runtime. In addition, we describe a cloud-ready solution, called EDA analytics central, for the continuous optimization of a design across an EDA flow. We used this system in building our runtime prediction model.
TL;DR: A computer‐aided design (CAD) tool dedicated for the design and simulation of Radiofrequency (RF) filters that are integrated into Advanced Design System (ADS) software that includes a graphical user interface developed using the design kit feature available under ADS and “Application Extension Language (AEL)” as a programming language.
Abstract: In this paper, we propose a computer‐aided design (CAD) tool in the electronic design automation (EDA) domain. This tool is dedicated for the design and simulation of Radiofrequency (RF) filters that are integrated into Advanced Design System (ADS) software. It includes a graphical user interface (GUI) developed using the design kit feature available under ADS and “Application Extension Language (AEL)” as a programming language. This will extend the existing smart filter design tool under ADS by adding more types of RF filters. The proposed feature will provide to users a rapid and an accurate tool to design and simulate RF filters by presenting interactive menus facilitating the process. As a proof of concept, an application of this tool is presented for the design of a Dual‐Behavior Resonators filter. The tool can be upgraded by adding other RF components and even entire front‐end circuits. In a future step, this tool will be enhanced by adding tuning capabilities to RF filters using ideal capacitors and varactors, which will make it the first one of its kind in the literature.
01 Jul 2022
TL;DR: Wu et al. as mentioned in this paper proposed LOSTIN, which exploits hybrid graph neural networks (GNNs) to provide highly accurate quality-of-result (QoR) estimations with great generalization capability.
Abstract: Despite the recent progress on machine learning (ML) based performance modeling, two major concerns that may impede production-ready ML applications in electronic design automation (EDA) are the stringent accuracy requirements and the generalization capability. To address these challenges, we a propose novel approach, namely LOSTIN 1 1 LOSTIN.com is a travel guide service to help people who visit a new city stay away from tourist traps and have a high-quality city tour. We envision our proposed LOSTIN would help the ML-based logic synthesis achieve high quality-of-results (QoR)., which exploits hybrid graph neural networks (GNNs) to provide highly accurate quality-of-result (QoR) estimations with great generalization capability, specifically targeting logic synthesis optimization. The key idea is to simultaneously leverage spatio-temporal information from hardware designs and logic synthesis flows to forecast performance (i.e., delay/area) of various synthesis flows on different designs. Specifically, the structural characteristics inside hardware designs are distilled and represented by GNNs; the temporal knowledge (i.e., the relative ordering of logic transformations) in synthesis flows can be imposed on hardware designs by combining a virtually added supernode or a sequence processing model with conventional GNN models. Evaluation on 3.3 million data points shows that the testing mean absolute percentage error (MAPE) on designs seen and unseen during training are no more than 1.2% and 3.1%, respectively, which are $\boldsymbol{7-15}\times$ lower than existing studies. Our dataset and ML models are publicly available at https://github.com/lydiawunan/LOSTIN.
13 Apr 2022
TL;DR: In this paper , the authors investigate the chip, package, and board co-design methodology with advanced packages and optical communication considering essential issues on physical design, electrical, thermal, and mechanical effects, timing, and testing, and suggest future research opportunities.
Abstract: As the design complexity grows dramatically in modern circuit designs, 2.5D/3D heterogeneous integration (HI) becomes effective for system performance, power, and cost optimization, providing promising solutions to the increasing cost of more-Moore scaling. In this talk, we investigate the chip, package, and board co-design methodology with advanced packages and optical communication considering essential issues on physical design, electrical, thermal, and mechanical effects, timing, and testing, and suggest future research opportunities. Layout: A robust and vertically integrated physical design flow for HI design is needed. We address chip-, package-, and board-level component planning, package-level RDL routing, board-level routing, optical routing, and placement and routing considering warpage and thermal effects. Timing: New chip-level and cross-chip timing analysis techniques are desired. We address timing propagation under current source delay model (CSM), timing analysis and optimization for optical-electrical routing, multi-corner multi-mode analysis for HI, hierarchical MCMM analysis. Testing: The scope covers functional-like test generation, System-in-Package (SiP) online testing, photonic integrated circuits (PIC) testing and design-for-test (DfT), etc. Integration: We shall address chip, package, and board co-design considering multi-domain physics, including physical, electrical, thermal, mechanical, and optical effects and optimization.
14 Mar 2022
TL;DR: In this paper , a product-level RTL-to-GDSII flow for the design of Adiabatic Quantum-Flux-Parametron (AQFP) electronic circuits is presented, with a focus on the special techniques used to comply with these challenges.
Abstract: Adiabatic superconducting devices are promising candidates to develop high-speed/low-power electronics. Advances in physical technology must be matched with a systematic development of comprehensive design and simulation tools to bring superconducting electronics to a commercially viable state. Being the technology fundamentally different from CMOS, new challenges are posed to design automation tools: library cells are controlled by multi-phase clocks, they implement the majority logic function, and they have limited fanout. We present a product-level RTL-to-GDSII flow for the design of Adiabatic Quantum-Flux-Parametron (AQFP) electronic circuits, with a focus on the special techniques used to comply with these challenges. In addition, we demonstrate new optimization opportunities for graph matching, resynthesis, and buffer/splitter insertion, improving the state-of-the-art.
TL;DR: In this article , a hybrid guided random search technique was proposed for multi-objective analog circuit optimization, where the non-dominated Sorting Genetic Algorithm 3 (NSGA-III) was adapted to the analog circuit sizing problem and combined with simulated annealing (SA) based singleobjective genetic algorithm (GA).
10 Jul 2022
TL;DR: PPATuner, a Pareto-driven physical design tool parameter tuning methodology, is proposed to achieve a good trade-off among multiple QoR metrics of interest at the physical design stage by incorporating the transfer Gaussian process (GP) model.
Abstract: Thanks to the amazing semiconductor scaling, incredible design complexity makes the synthesis-centric very large-scale integration (VLSI) design flow increasingly rely on electronic design automation (EDA) tools. However, invoking EDA tools especially the physical synthesis tool may require several hours or even days for only one possible parameters combination. Even worse, for a new design, oceans of attempts to navigate high quality-of-results (QoR) after physical synthesis have to be made via multiple tool runs with numerous combinations of tunable tool parameters. Additionally, designers often puzzle over simultaneously considering multiple QoR metrics of interest (e.g., delay, power, and area). To tackle the dilemma within finite resource budget, designing a multi-objective parameter auto-tuning framework of the physical design tool which can learn from historical tool configurations and transfer the associated knowledge to new tasks is in demand. In this paper, we propose PPATuner, a Pareto-driven physical design tool parameter tuning methodology, to achieve a good trade-off among multiple QoR metrics of interest (e.g., power, area, delay) at the physical design stage. By incorporating the transfer Gaussian process (GP) model, it can autonomously learn the transfer knowledge from the existing tool parameter combinations. The experimental results on industrial benchmarks under the 7nm technology node demonstrate the merits of our framework.
13 Apr 2022
TL;DR: It is shown that the dilemma that arises in analog design with the typical optimization processes employed for the synthesizing tasks is the root cause of the low level of automation in analogDesign.
Abstract: The vast majority of state-of-the-art integrated circuits are mixed-signal chips. While the design of the digital parts of the ICs is highly automated, the design of the analog circuitry is largely done manually; it is very time-consuming; and prone to error. Among the reasons generally listed for this is often the attitude of the analog designer. The fact is that many analog designers are convinced that human experience and intuition are needed for good analog design. This is why they distrust the automated synthesis tools. This observation is quite correct, but this is only a symptom of the real problem. This paper shows that this phenomenon is caused by very concrete technical (and thus very rational) issues. These issues lie in the mode of operation of the typical optimization processes employed for the synthesizing tasks. I will show that the dilemma that arises in analog design with these optimizers is the root cause of the low level of automation in analog design. The paper concludes with a review of proposals for automating analog design.
TL;DR: Monolithic 3D (M3D) is an emerging heterogeneous integration technology that overcomes the limitations of the conventional through-silicon-via (TSV) and provides significant performance uplift and... as mentioned in this paper.
Abstract: Monolithic 3D (M3D) is an emerging heterogeneous integration technology that overcomes the limitations of the conventional through-silicon-via (TSV) and provides significant performance uplift and ...
TL;DR: In this article , the current state of photonic design automation in terms of device modeling methods and circuit simulation methodologies, and compare the photonics design flow with mature electronic design automation design flows.
30 Oct 2022
TL;DR: The International Computer-Aided Design Conference (ICDAD) as discussed by the authors is the premier forum to explore new challenges, present leading-edge innovative solutions, and identify emerging technologies in the Electronic Design Automation (EDA) research areas.
Abstract: Jointly sponsored by ACM and IEEE, ICCAD is the premier forum to explore new challenges, present leading-edge innovative solutions, and identify emerging technologies in the Electronic Design Automation (EDA) research areas. ICCAD covers the full range of Computer-Aided Design (CAD) topics - from device and circuit-level up through system-level, as well as post-CMOS design.