Showing papers on "Electroplating published in 1998"

Method of forming copper/copper alloy interconnection with reduced electromigration

Abstract: The electromigration of a Cu or Cu alloy interconnection member is reduced by annealing the seed layer before electroplating or electroless plating the Cu or Cu alloy interconnection member on the seed layer. Embodiments include depositing a Cu or Cu alloy seed layer, annealing at about 100° C. to about 400° C. to increase the grain size of the seed layer and impart a (111)-dominant crystallographic option before plating the Cu or Cu alloy interconnect member thereon the seed layer

Some recent topics in gold plating for electronics applications

Abstract: A review is presented of selected recent topics in electrolytic and electroless gold plating for electronics applications. The topics covered include developments of non-cyanide electroplating baths for plating soft gold suitable for fabricating microbumps on silicon wafers, electroplating of hard gold and alternative materials with thermally stable electrical contact resistance and wear resistance for use on connectors exposed to elevated temperatures, and neutral, non-cyanide electroless processes for plating pure, soft gold on isolated areas of circuit boards. The development of the new electroless processes has been a subject of great interest and activity, and therefore an extensive survey of the progress in this field is included.

Self-encapsulated copper metallization

Abstract: Copper or copper alloy interconnection patterns are formed by a damascene technique. An aluminum or magnesium alloy is deposited in a damascene opening formed in a dielectric layer. Copper or a copper alloy is then electroplated or electroless plated on the aluminum or magnesium alloy, filling the opening. During low temperature annealing, aluminum or magnesium atoms diffuse through the copper or copper alloy layer and accumulate on its surface forming a self-encapsulated oxide to prevent corrosion and diffusion of copper atoms.

Electroplating system having auxiliary electrode exterior to main reactor chamber for contact cleaning operations

Abstract: A system for electroplating a semiconductor wafer is set forth. The system comprises a first electrode in electrical contact with the semiconductor wafer and a second electrode. The first electrode and the semiconductor wafer form a cathode during electroplating of the semiconductor wafer. The second electrode forms an anode during electroplating of the semiconductor wafer. A reaction container defining a reaction chamber is also employed. The reaction chamber comprises an electrically conductive plating solution. At least a portion of each of the first electrode, the second electrode, and the semiconductor wafer contact the plating solution during electroplating of the semiconductor wafer. An auxiliary electrode is disposed exterior to the reaction chamber and positioned for contact with plating solution exiting the reaction chamber during cleaning of the first electrode to thereby provide an electrically conductive path between the auxiliary electrode and the first electrode. A power supply system is connected to supply plating power to the first and second electrodes during electroplating of the semiconductor wafer and is further connected to render the first electrode an anode and the auxiliary electrode a cathode during cleaning of the first electrode.

Uniform electroplating of wafers

Abstract: The non-uniformity of electroplating on wafers is due to the appreciable resistance of the thin seed layer and edge effects. Mathematical analysis of the current distribution during wafer electroplating reveals that the ratio between the resistance of the thin deposited seed layer and the resistance of the electrolyte and the electrochemical reaction determines the uniformity of the electroplated layer. Uniform plating is critical-in-wafer metallization for the subsequent step of chemical mechanical polishing of the wafer. Based on the analysis, methods to improve the uniformity of metal electroplating over the entire wafer include increasing the resistance of the electrolyte, increasing the distance between the wafer and the anode, increasing the thickness of the seed layer, increasing the ionic resistance of a porous separator placed between the wafer and the anode, placement of a rotating distributor in front of the wafer, and establishing contacts at the center of the wafer. The rotating distributor generates multiple jets hitting the surface of the wafer, thus ensuring conformal electroplating. The jets can be either submerged in the electrolyte or above the level of the electrolyte. The shape and uniformity of the electroplated layer can be also determined by the shape and relative size of the counter-electrode (anode), by masking the edge of the wafer and by periodically reversing the plating current. The problem of uniformity is more severe as the diameter of the wafer becomes larger.

Electric potential shaping apparatus for holding a semiconductor wafer during electroplating

Abstract: Apparatus for treating the surface of a substrate, the apparatus comprising a clamshell (32) mounted on a rotatable spindle (40). The clamshell comprises a cone (34), a cup (36) and a flange (48). The flange (48) has apertures (50) which are adjacent the substrate or wafer (38) allowing gas bubbles entrapped on the substrate surface to readily escape.

Preparation of oxygen evolving electrodes with long service life under extreme conditions

Abstract: Among the numerous base metals tested for DSA® type electrodes (e.g., titanium and its alloys, zirconium, niobium etc.), tantalum is a potentially excellent substrate owing to its good electrical conductivity and corrosion resistance, and the favourable dielectric properties of its oxide. Nevertheless, a DSA® type electrode fabricated on a tantalum substrate would be very expensive due to the high cost of the metal. To prepare an anode combining the excellent properties of tantalum at reasonable price, a new material has been developed in our laboratory. This consists of a common base metal (e.g., Cu) covered with a thin tantalum coating. This tantalum layer was obtained by molten salt electroplating in a LiF–NaF–K2TaF7 melt at 800°C. Thus, an anode of the type Metal/Ta/Ta2O5–IrO2 with a surface load of 22gm-2 IrO2, submitted to the severe test conditions used in this work, exhibits a standardized lifetime tenfold greater than one made with ASTM grade 4 titanium base metal. Thus, this type of electrode might be advantageously employed as an oxygen evolution anode in acidic solutions.

Electroplating apparatus and process for reducing oxidation of oxidizable plating anions and cations

Abstract: An electroplating apparatus and method reduces oxidation of thermodynamically unstable and oxidizable ionic species in an electroplating solution to deposit complex magnetic alloy onto substrates. The electroplating apparatus comprises an electroplating cell (30) in which oxidation of oxidizable anions and cations is reduced. The cell comprises an anode compartment (110) with anolyte solution in contact with the anode (55), a cathode compartment (105) with catholyte solution containing oxidizable plating anions in contact with the cathode (50). A cation selective membrane (100) separates the electrode compartments. Upon application of a voltage or power supply (90) across the anode and cathode, the transport of oxidizable plating anions and to a lesser degree cations, to the anode is substantially blocked by the cation-selective semi-permeable membrane, thereby reducing oxidation of the oxidizable anions and cations at the anode. The concentration of the anolyte and catholyte solutions can be tailored, and an inert gas can be maintained above the electrolyte solution in an enclosed region (140) to further reduce oxidation.

Copper metallization of silicon wafers using insoluble anodes

Abstract: A plating system (10) and method are provided for electroplating silicon wafers with copper using an insoluble anode (13) wherein the electrolyte is agitated or preferably circulated through an electroplating tank (11) of the system and a portion of the electrolyte is removed from the system when a predetermined operating parameter is met. A copper-containing solution having a copper concentration greater than the copper concentration of the removed portion is added to the copper plating system (10) simultaneously or after electrolyte removal, in a substantially equal amount to the electrolyte removed from the system and balances the amount of copper plated and removed in the removal stream. In a preferred method and system, an electrolyte holding tank (19) is provided which serves as a reservoir for circulating electrolyte. The addition of the copper-containing solution and removal of working electrolyte is also preferably made from the holding tank (19). The preferred apparatus is preferably cylindrical and is specially configured so that recirculating electrolyte enters near the anode (13) and exits near the cathode (12) with the outlet of the apparatus having a substantially continuous opening around the periphery of the electroplating tank (11) so that electrolyte exiting the tank has a substantially uniform flow across the surface of the cathode (12). The anode (13) is preferably circular and has a central through opening (13a) through which the entering electrolyte passes.

Method of electroplating a copper or copper alloy interconnect

Abstract: Copper or a copper alloy is electroplated to fill via/contact holes and/or trenches in a dielectric layer. A barrier layer is initially deposited on the dielectric layer lining the hole/trench. A thin conformal layer of copper or a copper alloy is sputter deposited on the barrier layer outside the hole/trench. Copper or a copper alloy is then electroplated on the conformal copper or copper alloy layer and filling the hole/trench. During electroplating, the barrier layer functions as a seed layer within the hole/trench while the sputter deposited conformal copper or copper alloy layer enhances the flow of electrons from the wafer edge inwardly to provide a favorable deposition rate.

A method for preventing electroplanting of copper on an exposed surface at the edge exclusion of a semiconductor wafer

Abstract: A method for forming a copper interconnect (54) begins by depositing a barrier layer (48). An intermediate layer (50) is formed over the barrier layer (48) by exposing the barrier layer (48) to a plasma silane environment. The layer (50) is conductive when deposited so that contact resistance is not affected. The layer(50) is insitu covered with a copper seed layer (52). The layer (52) is not formed in an edge exclusion region (20) thereby exposing a portion (50a) of the layer (50). This portion (50a) will natively oxidize in a room ambient to form a copper electroplating prevention barrier whereby copper will not electroplate in the region (20). Therefore, the region (50a) prevents barrier-to-copper interfaces to avoid delamination of the copper while preserving the edge exclusion region desired for copper electroplating.

Sputter deposition and annealing of copper alloy metallization M

Abstract: Copper and a small amount of an alloying metal such as magnesium or aluminum are cosputtered onto a substrate having oxide on at least a portion of its surface. Either the wafer is held at an elevated temperature during deposition or the sputtered film is annealed without the wafer being exposed to ambient. Due to the high temperature, the alloying metal diffuses to the surface. If a surface is exposed to a low partial pressure of oxygen or contacts silicon dioxide, the magnesium or aluminum forms a thin stable oxide. The alloying metal oxide encapsulates the copper layer to provide a barrier against copper migration, to form an adhesion layer over silicon dioxide, and to act as a seed layer for the later growth of copper, for example, by electroplating.

Metal deposition into a porous silicon layer by immersion plating: Influence of halogen ions

Abstract: Metal deposition into a porous silicon (PS) layer by immersion plating has been studied. Ag and Cu were found to deposit on PS, while Ni was found not to deposit. The dependence of the amount of Cu deposition on Cu2+ concentration, halogen ion concentration, and immersion time was investigated using chelatometric titration. Copper deposition from halide solutions exhibited an unusual behavior; the amount increased with increasing concentration, then decreased, and no copper deposited at high concentration. This is because adsorption of chloride and bromide ions inhibits the copper deposition process. We have also discussed the metal deposition mechanism on the basis of x-ray diffraction, Fourier transform infrared spectroscopy, and x-ray photoelectron spectroscopy measurements. They revealed that metal deposition occurred simultaneously with the oxidation of silicon to SiO2. Copper crystals 30–80 nm in diameter deposited on the oxidized PS surface rather than on the unoxidized PS surface.

Methods of electroplating solder bumps of uniform height on integrated circuit substrates

Abstract: Methods of electroplating solder bumps of uniform height on integrated circuit substrates include the steps of drawing plating current through an integrated circuit wafer by electrically shorting an integrated circuit's ground, power and signal pads together using an ultra-thin plating base layer (e.g., <0.075 μm thick) and then using a backside wafer contact to draw electroplating current along parallel paths which extend through the ground and signal pads and into the substrate. The ground pads are preferably electrically coupled to the substrate at substrate contact regions (e.g., N + or P + diffusion regions) and the signal pads are preferably electrically coupled to the substrate through active semiconductor devices (e.g., FETs, BJTs, . . . ) to which the signal pads are attached. Plating current is preferably drawn in parallel through an integrated circuit's active semiconductor devices and substrate contact regions. The combined contributions of the plating currents drawn through the substrate contact regions and the active semiconductor devices is sufficient to maintain the plating base layer and underlying pads at uniform potentials even though the plating base layer has a preferred thickness of less than about 0.075 μm. These uniform and typically non-zero potentials cause the rates of electroplating to be highly uniform across the wafer by limiting lateral current flow through the plating base layer. The uniformity of the electroplated solder bumps can also be enhanced by using high density controlled collapse chip connection (C4) ("flip-chip") technologies and by interspersing the ground and signal pads on each "flip-chip" so that each signal pad has at least one ground pad as a nearest neighbor.

Method of forming reliable capped copper interconnects

Abstract: The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper silicide layer thereon; or (b) with an ammonia plasma followed by reaction with silane or dichlorosilane to form a copper silicide layer thereon. The diffusion barrier layer is then deposited on the copper silicide layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the copper silicide layer thereon, and depositing a silicon nitride diffusion barrier layer on the copper silicide layer.

X-ray photoelectron spectroscopy characterization of the oxidation of electroplated and sputter deposited copper surfaces

Abstract: X-ray photoelectron spectroscopy (XPS) was used to study the surface oxidation of sputtered and electroplated copper films following exposure to ambient air and chemical processing reagents used during the fabrication of interconnect structures. Exposure of both sputtered and electroplated copper films to ambient air and deionized (DI) water resulted in the formation of thin copper oxide layers. For ambient exposed copper films, the topmost layer contains Cu2+ oxide species, and the next Cu+ oxides. For DI water exposure, only Cu+ oxide species were observed. Oxidation was more rapid for the electroplated compared to the sputtered copper films as measured by copper oxide to copper metal concentration ratios calculated from XPS curve fitting results and photon-induced Auger peak height measurements. For the electroplated copper films, oxygen uptake was slower as a result of exposure to ambient compared to DI water treatments. Electroplated copper films exposed to common wet chemical etchants also show indi...

Copper interconnect with improved electromigration resistance

Abstract: Capping layer adhesion to a Cu or Cu alloy interconnect member is enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with a hydrogen plasma to substantially reduce oxides thereon, forming a thin layer of copper silicide on the treated surface and depositing the capping layer thereon. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric layer, chemical-mechianiical polishing, hydrogen plasma treatment, reacting the treated surface with silane or dichlorosilane to form a layer of copper silicide on the treated surface and depositing a silicon nitride capping layer on the thin copper silicide layer.

Effect of brighteners on hydrogen evolution during zinc electroplating from zincate electrolytes

Abstract: Hydrogen evolution during zinc electrodeposition on a steel substrate from zincate electrolytes containing different additives was studied using various experimental techniques.The hydrogen evolution reaction is limited by the electron transfer step. Hydrogen evolution is most intensive during the first seconds from the beginning of electrodeposition due to the lower overpotential of hydrogen on steel as compared with that on zinc. The evolved hydrogen is dissipated in three ways. Most is dissipated to the atmosphere via gas bubbles at a constant rate. Some is dispersed in the electrolyte some diffuses into the steel substrate, predominantly at the commencement of deposition. The additives affect both the total amount of evolved hydrogen and its distribution. The highest amount of hydrogen is evolved in the presence of the anisaldehyde bisulphite containing composite additive. The highest amount of hydrogen included in the substrate and remaining in the electrolyte corresponds to the use of the Na–N-benzylnicotinate containing additive. In this case blistering is observed.

Process for applying protective and decorative coating on an article

Abstract: A method for depositing a multi-layered protective and decorative coating on an article comprising first depositing at least one coating layer on the article by electroplating, removing the electroplated article from the electroplating bath and subjecting it to pulse blow drying to produce a spot-free surface on the electroplated article, and then depositing, by physical vapor deposition, at least one vapor deposited coating layer on the electroplated article. The electroplated layers are selected from copper, nickel and chrome. The physical vapor deposited layers are selected from non-precious refractory metals, non-precious refractory metal alloys, non-precious refractory metal compounds, and non-precious refractory metal alloy compounds.

Multilevel microstructure fabrication using single-step 3D photolithography and single-step electroplating

Abstract: We developed a useful method to obtain multilevel microstructures simply by single-step 3D photolithography followed by single-step electroplating. By varying UV exposure depth with multiple photomasks in a single-coated conventional thick photoresist, we form multilevel photoresist molds in a single lithography step. After the 3D mold patterning, metal electroplating is performed on it until 3D metallic microstructures are obtained. The critical issue in this process, the exposure depth control, was carefully examined by observing the exposure time versus development characteristic of the resist, in the film thickness range of 40 to 90 micrometer. We proposed a simple method to reproducibly obtain the resist thickness of each level as designed. Using the unique overplating feature in electroplating process, we demonstrated two utmost practical examples: a unified Orifice Plate Assembly (OPA), which has orifice, channel, and reservoirs in a single body, for high-resolution inkjet printhead, and an electroplated Solenoid-type Integrated Inductor (SI 2 ). Both were fabricated using a single-coated 80 micrometer-thick photoresist with only two photomasks, and have many advantages in productivity and performance. This method does not stack planar layer vertically to make 3D microstructures as in the conventional ways, therefore, is a simple, low-cost, and high-yield process. And also, it is IC compatible due to its low process temperature and monolithic process.

Method for protecting the edge exclusion of a semiconductor wafer from copper plating through use of an edge exclusion masking layer

Abstract: A method for forming a copper interconnect begins by depositing a barrier layer (48) within an in-laid region (18). An edge exclusion protection layer (50) is formed over the barrier layer (48), and this layer (50) is processed so that it only lies within the edge exclusion region (20) of the wafer. The layer (50) is removed from active area portions of the wafer so that contact resistance of copper interconnects is not affected. Wet surface processing is used to form a catalyst (64 b) on the wafer surface to enable electroless copper plating within active areas of the wafer to form a copper seed layer (52). The layer (52) is not formed in an edge exclusion region (20). Electroplating is then used to thicken the copper material to form a copper layer (54) over the layer (52) wherein the in-laid copper interconnect is completed.

Method for filling recessed micro-structures with metallization in the production of a microelectronic device

Abstract: A method for filling recessed micro-structures at a surface of a semiconductor wafer with metallization is set forth. In accordance with the method, a metal layer is deposited into the micro-structures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to substantially fill the recessed micro-structures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature to allow grain growth which provides optimal electrical properties.

A single step electroplating process for interconnect via fill and metal line patterning

Abstract: A single step electroplating process for interconnect via fill and metal line formation on a semiconductor substrate is disclosed. In this process, a barrier layer is formed onto a surface of a substrate (82) that has at least one via and then a conductive layer is formed onto the barrier layer (83). Next, a photoresist layer is applied and patterned on top of the conductive layer (84). The via plugs and metal lines are then deposited on the substrate simultaneously using an electroplating process (85). After the electroplating process is completed, the photoresist (86) and the conductive layer between the deposited metal lines are removed (87). The process provides a simple, economical and highly controllable means of forming metal interconnect systems while avoiding the difficulties associated with depositing and patterning metal by traditional semiconductor fabrication techniques.

Process for stabilizing organic additives in electroplating of copper

Abstract: A process and assembly for stabilizing organic additives in an electrolytic solution while electroplating copper. The process includes forming a protective film on a first surface of an anode and minimizing contact between the electrolytic solution and a second surface of the anode which is further from the cathode than the first surface. An anode housing is used to minimize contact between the electrolytic solution and the second surface of the anode. The housing includes two side walls and a bottom wall, each having a groove, and a sealing back plate. The anode is fitted in the grooves such that the first surface of the anode is in contact with the electrolytic solution and the second surface of the anode abuts against the sealing back plate. The anode housing may be used in an electroplating system including the anode housing, a plating tank containing the electrolytic solution, a cathode immersed in the electrolytic solution, and an anode, which preferably is in the shape of a slab.

Electrochemical process for advanced package fabrication

Abstract: Interconnections for high-end applications are essentially low-resistance transmission-line structures with precisely controlled cross-sectional shapes and dimensions. The relatively thick copper conductors-typically 6 µm or more-combined with the stringent control required on the 10-20-µm-wide cross sections stretches the capabilities of the subtractive etch and lift-off processes that are typically used in semiconductor fabrication to pattern evaporated and sputtered metal films. Electroplating through a photoresist mask, which has proven itself to be a highly effective, precision manufacturing process for thin-film magnetic recording heads, is, however, capable of meeting and far exceeding the requirements of package fabrication. This paper describes the fabrication of a package structure that integrates traditional dry-process technologies with electrolytic copper plating to form the conductors, polyimide backfill and planarization steps to form the dielectric, and electroless deposition to selectively clad the copper lines to prevent adverse reaction of the copper with water generated during the polyimide cure. The discussion highlights salient issues which are pertinent to the compatibility of the individual process steps and to the extension of the technology to more demanding packaging structures and to other applications.

Method for preparing composite membrane for separation of hydrogen gas

Abstract: A process for manufacturing a composite membrane for separation of hydrogen gas using palladium, which employs the step of electroplating under vacuum an alloy of a palladium compound and a transition metal.