Showing papers on "Filter capacitor published in 2003"

A comparative analysis of multiloop voltage regulation strategies for single and three-phase UPS systems

Abstract: Most of the many reported control algorithms for uninterruptible power supplies (UPSs) use either filter inductor or filter capacitor currents as feedback variables to regulate the output voltage. This paper explores the fundamental performance issues associated with the use of these quantities as feedback variables, with a view to determining their contribution to the transient system response and output harmonic compensation in any particular situation. A proportional plus resonant (P+resonant) compensator is then added into the outer voltage regulation loop to achieve zero steady error, to develop a high performance UPS control algorithm, which is applicable to both single-phase and three-phase systems. Theory, simulation, and experimental results are presented in the paper.

Capacitor charge balancing technique for a three-level PWM power converter

Abstract: A power converter includes a DC to AC inverter that is connected to a neutral node formed between first and second capacitors connected across two DC supply lines. The inverter is operated to selectively couple the DC supply lines and the neutral node to an output terminal thereby producing an alternating voltage waveform formed by a sequence of output pulses having positive, zero and negative voltage levels. To compensate for a voltage imbalance across the capacitors, an imbalance compensation coefficient is derived from the difference in voltages across the first and second capacitors and from the direction of current between the neutral node and the inverter. The imbalance compensation coefficient is employed to adjust the width of the output pulses so as to charge and discharge the capacitors to correct the imbalance.

EMI filterd connectors using internally grounded feedthrough capacitors

Abstract: An EMI filtered connector includes a plurality of conductive terminal pins, a grounded conductive connector housing through which the terminal pins pass in non-conductive relation, and an array of feedthrough filter capacitors. Each of the feedthrough filtered capacitors has a distinct first set of electrode plates, a non-distinct second set of electrode plates, and a first passageway through which a respective terminal pin extends in conductive relation with the first set of electrode plates. At least one ground lead is conductively coupled to the conductive connector housing and extends into a second passageway through the array of feedthrough filter capacitors in conductive relation with the second set of electrode plates. An insulator is disposed in or adjacent to the connector for mounting the conductive terminal pins for passage through the conductive connector with the conductive terminal pins and the connector in non-conductive relation. The outer peripheral surface of the array of feedthrough filter capacitors is non-conductive.

MIM capacitors and methods for fabricating same

Abstract: Semiconductor devices and methods for making the same are described in which a single high k or ferroelectric dielectric layer is used to form decoupling capacitors and analog capacitor segments. Analog capacitors are formed by coupling analog capacitor segments in series with one another, wherein the capacitor segments may be connected in reverse polarity relationship to provide symmetrical performance characteristics for the analog capacitors.

Ceramic chip capacitor of conventional volume and external form having increased capacitance from use of closely spaced interior conductive planes reliably connecting to positionally tolerant exterior pads through multiple redundant vias

Abstract: A capacitor including at least one interior metallization plane or plate and a multiplicity of vias for forming multiple redundant electrical connections within the capacitor. Series capacitors are provided having at least two interior plates redundantly electrically connected to at least two respective exterior plates. R-C devices are provided having multiple redundant vias filled with resistor material and/or conductor material to provide a resistor either in series with or parallel to a capacitor. Capacitors and R-C devices are provided having end terminations for applying voltage differential. Further, a method for making single capacitors, multiple parallel array capacitors, series capacitors and R-C devices is provided in which the chips are formed from the bottom up.

Ripple current cancellation circuit

Abstract: A ripple current cancellation technique injects AC current into the output voltage bus of a converter that is equal and opposite to the normal converter ripple current. The output current ripple is ideally zero, leading to ultra-low noise converter output voltages. The circuit requires few additional components, no active circuits are required. Only an additional filter inductor winding, an auxiliary inductor, and small capacitor are required. The circuit utilizes leakage inductance of the modified filter inductor as all or part of the required auxiliary inductance. Ripple cancellation is independent of switching frequency, duty cycle, and other converter parameters. The circuit eliminates ripple current in both continuous conduction mode and discontinuous conduction mode. Experimental results provide better than an 80/spl times/ ripple current reduction.

Printed circuit board with embedded capacitors and manufacturing method thereof

Abstract: Disclosed is a printed circuit board which is advantageous in terms of high capacitance by embedding capacitors comprising polymer capacitor pastes with high-dielectric constant coated on an inner layer of the printed circuit board and then semi-dried to a state of B-stage.

Ramp generation with capacitors

Abstract: A ramp generator includes an array of capacitors having a common top plate that provides a ramp output signal. Each of the capacitors has a bottom plate switched sequentially between a low reference voltage and a high reference voltage in response to a value in a shift register. For an upward ramp, capacitors can be switched to their high reference voltages in succession, increasing the output voltage on the common top plate; for a downward ramp, capacitors can be switched to their low reference voltages in succession, decreasing the output voltage. The capacitors can be switched by a multi-bit shift register, each bit of which controls one capacitor's voltage. Each time a clock signal is applied to the shift register, a value in the shift register shifts another capacitor between its low and high reference voltages.

Influence of grading capacitors on the breaking performance of a 24-kV vacuum breaker series design

Abstract: This paper deals with the breaking capability of a series design consisting of two 24-kV vacuum circuit breakers (VCB) with grading capacitors. The investigations were done under worst-case conditions with regard to the rate of rise of the transient recovery voltage (TRV) exceeding the values given in the relevant IEC standard. In previous publications it was shown that the breaking capability of the series arrangement is higher than doubling the voltage of a single tube. In addition to these results it is shown that in some cases grading capacitors can increase the breaking capacity even more. Tests with simultaneous opening of the contacts of both tubes are presented with the application of different grading capacitors as well as the choice of different arcing times. In the case of reignition of one of the tubes the current circulating between the two tubes is shown. As a result of the tests the breaking capability of the arrangement depending on the arcing time and the value of the grading capacitors can be classified into three zones: area of reignition of the arrangement, scatter area and area of successful arc quenching.

Novel modulation schemes minimizing the switching losses of sparse matrix converters

Abstract: The switching losses of a three-phase sparse matrix converter (SMC) operating in the lower modulation range are minimized by employing the lowest and the second largest input line-to-line voltage for the formation of the converter DC link voltage. The resulting current stresses on the power semiconductors and the switching frequency ripple RMS values of the filter capacitor voltages and output currents are calculated by digital simulation and compared to conventional modulation. Finally, a modulation scheme is introduced which allows the generation of reactive input power also for missing active power transfer via the DC link and/or purely reactive load. This is a basic requirement for operating the SMC in boost mode where the output filter capacitor voltages have to be controlled sinusoidally also for no-load operation.

A study of series‐parallel changeover circuit of a capacitor bank for an energy storage system utilizing electric double‐layer capacitors

Abstract: Electric double-layer capacitors showing a remarkably high energy density (compared with conventional electrolytic capacitors) are now under development. Capacitors of this type have significant advantages, namely, high durability against repeated charge and discharge and no need for maintenance. Therefore, we have studied feasible basic circuit configurations and control methods required to apply electric double-layer capacitors as an energy storage element in output-power leveling systems for solar cells or windmill power generators, and in uninterruptible power supply systems. This paper discussed operating methods for a capacitor bank to improve the efficiency. High efficiency has been demonstrated by the simulations and the experiments. © 2003 Wiley Periodicals, Inc. Electr Eng Jpn, 145(3): 33–42, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/eej.10155

On-chip decoupling capacitor optimization for noise and leakage reduction

Abstract: The on-chip decoupling capacitors are widely used in today's high-performance microprocessor design to mitigate the power supply noise problem. The continued reduction of oxide thickness in advanced nanotechnology, however, also significantly increases the tunneling current and leakage power of thin-oxide capacitors. This paper describes the modeling and simulation of a complete chip and package power supply distribution network, and the optimization of the placement of thin-oxide and thick-oxide capacitors to reduce the tunneling current, leakage power, and burn-in cost, while limiting the power supply noise within noise margin.

Charge balancing circuit

Abstract: A charge balancing circuit is disclosed that is configured to provide charge balancing for a bank of series connected charge storage devices such as capacitors One embodiment of the charge balancing circuit comprises a voltage divider, an operational amplifier, and a negative feedback resistor connected between every two capacitors The circuit is configured to monitor the voltage in each of the capacitors and, if the voltage in one of the capacitors is higher than the other, the circuit transfers energy from the higher charged capacitor to the lower charged capacitor until the capacitors are balanced A current limiting resistor can be included for limiting the output current of the operational amplifier to a safe value and for providing feedback information regarding the health of the capacitor An additional gain stage can also be included for increasing the output current of the operational amplifier for banks of large charge storage devices such as capacitors

Memory cell capacitors having an over/under configuration

Abstract: Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second capacitor such that at least a portion of the second capacitor is underlying the first capacitor. Such memory cell capacitors can thus have increased surface area for a given capacitor height versus memory cell capacitors formed strictly laterally adjacent one another. The memory cell capacitors can be fabricated using silicon-on-insulator (SOI) techniques. The memory cell capacitors are useful for a variety of memory arrays, memory devices and electronic systems.

Semiconductor capacitor device having reduced voltage dependence

Abstract: A semiconductor capacitor device has two pairs of first and second MIM capacitors on a semiconductor substrate. The paired first and second MIM capacitors include respective capacitor dielectric films having different compositions. Also, the paired first and second MIM capacitors are connected in inverse parallel fashion, with an upper electrode of the first MIM capacitor being connected with a lower electrode of the second MIM capacitor and with a lower electrode of the first MIM capacitor being connected with an upper electrode of the second MIM capacitor. Furthermore, the two first MIM capacitors are electrically connected in inverse parallel with each other, and the two second MIM capacitors are also electrically connected in inverse parallel with each other. This arrangement facilitates mutual counteraction of the voltage dependences of the two pairs of first and second MIM capacitors so as to make the voltage dependence of the capacitance of the capacitor device small.

Filters with inductance cancellation using printed circuit board transformers

Abstract: Capacitor parasitic inductance often limits the high-frequency performance of filters for power applications. However, these limitations can be overcome through the use of specially-coupled magnetic windings that effectively nullify the capacitor parasitic inductance. This paper explores the use of printed circuit board (PCB) transformers to realize parasitic inductance cancellation of filter capacitors. Design of such inductance cancellation transformers is explored, and applicable design rules are established and experimentally validated. The high performance of the proposed inductance cancellation technology is demonstrated in an EMI filter design.

Advanced modulation scheme for three-phase three-switch buck-type PWM rectifier preventing mains current distortion originating from sliding input filter capacitor voltage intersections

Abstract: Modulation schemes for three-phase three-switch buck-type PWM rectifiers where the switching state of one bridge leg is clamped within a /spl Pi//3-wide interval of the mains period do guarantee minimum switching losses as well as minimum input filter capacitor voltage ripple and minimum DC current ripple. However, as shown in this paper by a detailed analysis of the time behavior of the input filter capacitor voltages within a pulse period such modulation schemes are characterized by the occurrence of sliding intersections of the filter capacitor voltages which do cause input current distortion. An advanced modulation scheme is proposed which does prevent the input current distortion and does allow to maintain the optimum performance of conventional modulation schemes.

A linear high voltage charge pump for MEMs applications in 0.18/spl mu/m CMOS technology

Abstract: Tunable MEMS components start to appear in wireless communication systems. They allow for new functionality such as tunable RF filters or they improve performance like electrostatically tuned variable capacitors that are used in voltage-controlled oscillators. However, the required tuning voltage for these capacitors is often much higher than the supply voltage of these capacitors is often much higher than the supply voltage of the deep sub-micron (Bi)CMOS technology which is typically used for these applications. Therefore we designed a high voltage charge pump that can generate an output voltage between -0.7V and +14.8 V out of a 1.8 V power supply. It is built in a 0.18 /spl mu/m CMOS technology, requires the same control signals as a regular charge pump and provides a constant output current of 0.7/spl mu/A over its complete voltage range of MEMS variable capacitors at low power, at a small area cost and in a way which is completely transparent to the system designer.

Variable RF MEMS capacitors with extended tuning range

Abstract: Three distinct designs of variable RF MEMS capacitors are presented and a comparison is made in terms of their continuous tuning range. Among these designs are the classical parallel-plate capacitor, as well as the so-called two-gap structure and a novel device with torsion-beam suspensions and double actuation. This allows the capacitance to be tuned over a larger range compared to a single-driven device. As a result of this, the tuning range of the device exceeds the theoretical 50%-limit for parallel-plate capacitors. The tuning ranges of all three devices have been determined experimentally and were found to be 39% for the parallel-plate capacitor, 310% for the two-gap structure and 61% for the torsion-suspension device. The measured tuning voltages are 17 V, 22 V and 11 V respectively.

Power supply device

Abstract: PROBLEM TO BE SOLVED: To provide a power supply device which is capable of, when the main power supply is interrupted, consuming electric charges accumulated in a filter capacitor in a short time without use of a resistor for discharge or a dedicated circuit for discharge and without causing thermal destruction in switching transistors. SOLUTION: The power supply device comprises the filter capacitor 14 which filters direct-current voltage; and an inverter device 11. In the inverter device, a pair of the switching transistors 1 and 2 are connected in series to constitute an arm in at least one phase. The inverter device is fed with the filtered voltage, and controls turn-on/off of the switching transistors and thereby outputs predetermined alternating-current voltage. The power supply device is provided with a driving means 8 which simultaneously turns on the switching transistors in the arm in at least one phase. If direct-current voltage is interrupted, the power supply lets an arm short-circuiting current through the switching transistors which have been turned on by the driving means, and the electric charges accumulated in the filter capacitor are consumed. COPYRIGHT: (C)2004,JPO

Method to improve charge pump reliability, efficiency and size

Abstract: A dynamic clamp is used in conjunction with capacitors with thinner dielectric or with deep trench capacitors to solve the problem of dielectric breakdown in high stress capacitors. The dynamic clamp is realized using a two stage pump operation cycle such that, during a first stage pump cycle, a middle node of a pair of series connected capacitors is pre-charged to a supply voltage and, during a second stage pump cycle, the middle node is coupled by a boost clock. Thus, at any moment in the pump operation cycle, the voltage across the capacitors is held within a safety range.

High-Q integrated RF passives and micromechanical capacitors on silicon

Abstract: The PASSI/spl trade/ technology platform is described for the integration of low-loss inductors, capacitors, and MEMS on high-ohmic Si substrates. Using this platform the board space area taken up by e.g. impedance matching circuits can be reduced by 50%. The losses of passives induced by the semi-conducting Si substrate can effectively be suppressed using a combination of surface amorphisation and e-beam irradiation. The incorporation of MEM tuneable capacitors in high-Q inductor-capacitor networks is demonstrated.

Frequency-dependent characterization of bulk and ceramic bypass capacitors

Abstract: Power distribution networks (PDN) use various kinds of capacitors to create the required impedance profile and to suppress noise. The simple model of bypass capacitors is a series R-L-C network with frequency independent parameters. The paper gives measured data for various bulk and ceramic capacitors, showing the extraction procedure and frequency dependent data of all three parameters. Various physical contributors to the frequency dependencies are identified. From low frequencies up to SRF (series resonance frequency), capacitance can drop as much as 60%. Inductance should be measured in a small PCB fixture with planes, vias and pads representing the intended application. The added inductance due to the capacitor body is shown to be fairly independent of via length connecting to the nearest planes.

Impact of capacitor dielectric relaxation on a 14-bit 70-MS/s pipeline ADC in 3-V BiCMOS

Abstract: In this paper, phenomena of charge absorption and relaxation in the plasma enhanced chemical vapor deposition (PECVD) silicon nitride dielectric (Si/sub 3/N/sub 4/) used in the capacitors of a 45-GHz f/sub T/, 0.4-/spl mu/m L/sub min/ SiGe BiCMOS are observed and interpreted. When such capacitors are used to design a pipelined 14-bit 70-MS/s switched-capacitor analog-to-digital converter (ADC), dielectric relaxation is identified as the cause of 8-LSB-wide gaps in the integral nonlinearity, which leads to the degradation of the converter performance even at low frequencies. The effect has been analyzed via Matlab behavioral simulations and SPICE circuit simulations. Ad-hoc experimental tests aimed at detecting residual amounts of charge left in the capacitors as a memory of previous states have been also carried out. After low-density low-pressure chemical vapor deposition (LPCVD) oxide capacitors (SiO/sub 2/) are introduced in the process, a new ADC test chip delivers 72.5-dBFS SNR, 82-dBc SFDR, 11.7-bit ENOB at 70 MS/s and 1-MHz input. The circuit features a die size of 5.3 /spl times/ 5.3 mm/sup 2/ and dissipates 1 W from the 3.3-V supply.

High energy density pulsed power capacitors

Abstract: Pulsed power in mobile systems requires high energy density capacitors as energy storage and power compression devices. Applications range from medical defibrillators to naval artillery, with a wide envelope of operating conditions requiring several technology approaches. The ongoing, multifaceted development effort on high energy density pulsed power capacitors at General Atomics Energy Products has yielded capacitors with significantly higher energy densities (> 5 J/cc) than were available a few years ago. Substantially higher energy densities are also being achieved in capacitors designed for microsecond discharge applications. This paper describes this progress and the state of the art in pulsed power capacitors.

Manufacturing technology effect on current pulse handling performance of metallized polypropylene film capacitors

Abstract: In this paper, the testing of the pulse-withstanding capability of metallized polypropylene film (MPPF) capacitors is reported. Four groups of capacitors having the same electrical characteristics but different geometry were considered for the test. Capacitors with long geometry seem to have poorer pulse handling performance for similar electrical stress conditions. However, the premature failure of one of the capacitor groups tested suggests that the quality of the end-edge contact is strongly dependent on the physical features of the manufacturing process. The end-edge contact plays a vital role in the current pulse handling capability of MPPF capacitors, which varies from a few hundred to several thousand discharging cycles depending on the geometry of the capacitor and the end-edge contact manufacturing process.

Active damping of oscillations in LC-filter for line connected, current controlled, PWM voltage source converters

Abstract: Presented is a method for active damping of oscillations between line reactance and filter capacitors in LC-filter for line connected current controlled pulse width modulated (PWM) voltage source converters. The idea is to include closed loop feedback control that controls the capacitor voltage oscillations to zero by adding damping components to the current references. The voltage oscillations are calculated from manipulated measured filter capacitor voltages (using phase locked loop (PLL), Park- and inverse Park-transformation, low pass filtering and summation). The advantage of such an approach is that the higher oscillation frequency components can be controlled independently of remaining converter control. It is only the higher frequency components that are controlled by this additional closed loop voltage control. Further, additional measurements and increased converter rating are not required. Simulations and measurements presented in this paper show that the method works as intended. If active damping is implemented, then the voltage quality at the point of converter connection is maintained also in cases were filter oscillations is to be expected when the LC-filter is introduced.

Apparatus and method for filtering voltage for an electrostatic precipitator

Abstract: An apparatus and method for controlling voltage applied to an electrostatic precipitator (66) is disclosed. This apparatus includes a pulsating, direct current, voltage mechanism that is operable to receive power from a single phase, alternating current voltage source, and a spiral wound filter capacitor (62), wherein the pulsating, direct current, voltage mechanism is electrically connected in parallel to the spiral wound filter capacitor (62) and the spiral wound filter capacitor (62) is electrically connected in parallel to the electrostatic precipitator (66). Optionally, a resistor (65) is present to lower the transient voltage rating of the spiral wound filter capacitor (62). A switching mechanism may be utilized to apply differing amounts of capacitance and inductance in order to apply a range of voltage waveforms to the electrostatic precipitator (66) to potentially maximize particulate collection efficiency for the electrostatic precipitator (66).

Method and system for improving quiescent currents at low output current levels

Abstract: An oscillator circuit is coupled to an enable pin of an Voltage regulator so that total power consumption is minimized in the application. A filter capacitor is coupled to the Voltage regulator such that current is supplied to the load (the application) while the Voltage regulator is disabled. The frequency of the oscillator circuit is low such that power consumption by the oscillator is minimal. The duty cycle (DC) of the oscillator circuit is selected so that the output voltage across the load does not drop below minimum voltage requirements in the application. The total current (I) that is consumed by the system corresponds to: I=DC*Idq+(1−DC)*Iq+Iosc+Iapp, where Iq corresponds to the shutdown current of the LDO, Idq is the ground current of the LDO, Iosc is the oscillator operating current, and Iapp is the average current consumed by the application.

Printed wiring boards having low inductance embedded capacitors and methods of making same

Abstract: A printed wiring board (PWB) has stacked innerlayer panels (1001, 1002, 1003, ...) comprised of passive circuit elements (105). The passive elements (105) can include capacitors with electrode terminations located within the footprints of the capacitor electrodes (170, 180). The capacitor terminations are therefore closely spaced, reducing the capacitors' contributions to loop inductance in the innerlayer. Capacitor terminations within the electrode footprints also reduce the PWB board surface area used in forming the capacitors. The capacitor terminations are connected by circuit conductors (1021, 1022).