Showing papers on "Hardware Trojan published in 2022"

Detecting Hardware Trojans in PCBs Using Side Channel Loopbacks

Abstract: Malicious modifications to printed circuit boards (PCBs) are known as hardware Trojans. These may arise when malafide third parties alter PCBs premanufacturing or postmanufacturing and are a concern in safety-critical applications, such as industrial control systems. In this research, we examine how data-driven detection can be utilized to detect such Trojans at run-time. We develop a flexible and reconfigurable PCB test bed derived from the popular open-source programmable logic controller (PLC) platform “OpenPLC.” We then develop a Trojan detection framework, which utilizes and analyzes multimodal side channels (e.g., timing, magnetic signals, power, and hardware performance counters). We consider defender-configurable input/output (I/O) loopback test, comparison with design-document baselines, and magnetometer-aided monitoring of system behavior under defender-chosen excitations. Our approach can extend to golden-free environments. Golden (known-good) versions of the PCBs are assumed not available, but design information, datasheets, and component-level data are available. We demonstrate the efficacy of our approach on a range of Trojans instantiated in the test bed.

Detecting Hardware Trojans Using Combined Self-Testing and Imaging

Abstract: Hardware Trojans are malicious modifications in integrated circuits (ICs) with an intent to breach security and compromise the reliability of an electronic system. This article proposes a framework using self-testing, advanced imaging, and image processing with machine learning to detect hardware Trojans inserted by untrusted foundries. It includes on-chip test structures with negligible power, delay, and silicon area overheads. The core step of the framework is on-chip golden circuit design, which can provide authentic samples for image-based Trojan detection through self-testing. This core step enables a golden-chip-free Trojan detection that does not rely on an existing image data set from Trojan-free chip or image synthesizing. We have conducted an in-depth analysis of detection steps and discussed possible attacks with countermeasures to strengthen this framework. The performance evaluation on a 28-nm FPGA and a 90-nm IC validates its high accuracy and reliability for practical applications.

Hybrid multi-level hardware Trojan detection platform for gate-level netlists based on XGBoost

Abstract: Coping with the problem of malicious third-party vendors implanting Hardware Trojan (HT) in the circuit design stage, this paper proposes a hybrid-mode gate-level hardware Trojan detection platform based on the XGBoost algorithm. This detection platform is composed of multi-level HT localization and circuit structure based HT detection. Each wire of the circuit is regarded as a node in multi-level HT localization, and static characteristics of nodes are analysed, combining with dynamic detection to locate HT. The network structure features of the circuit are extracted in modular HT structure detection, aiming to identify HT accurately and rapidly. The hybrid-mode HT detection platform can efficiently meet various detection requirements, such as HT localization or rapid and accurate HT detection. The experiment results on Trust-Hub benchmark show that the multi-level localization can achieve 94.0% location accuracy, and the modular HT structure detection accuracy can achieve 100%. The modular HT structure detection is about four times as fast as the multi-level HT localization on feature extraction. Therefore, multi-level localization and modular HT structure detection can be respectively or cooperatively applied for specific HT detection issues, which proves that the proposed hybrid-mode gate-level HT detection scheme is practical and effective.

Hardware Trojan Detection using Graph Neural Networks

Abstract: The globalization of the Integrated Circuit (IC) supply chain has moved most of the design, fabrication, and testing process from a single trusted entity to various untrusted third party entities around the world. The risk of using untrusted third-Party Intellectual Property (3PIP) is the possibility for adversaries to insert malicious modifications known as Hardware Trojans (HTs). These HTs can compromise the integrity, deteriorate the performance, and deny the functionality of the intended design. Various HT detection methods have been proposed in the literature; however, many fall short due to their reliance on a golden reference circuit, a limited detection scope, the need for manual code review, or the inability to scale with large modern designs. We propose a novel golden reference-free HT detection method for both Register Transfer Level (RTL) and gate-level netlists by leveraging Graph Neural Networks (GNNs) to learn the behavior of the circuit through a Data Flow Graph (DFG) representation of the hardware design. We evaluate our model on a custom dataset by expanding the Trusthub HT benchmarks trusthub1. The results demonstrate that our approach detects unknown HTs with 97% recall (true positive rate) very fast in 21.1ms for RTL and 84% recall in 13.42s for Gate-Level Netlist.

Golden-Free Hardware Trojan Detection Using Self-Referencing

Abstract: The globalization of the semiconductor supply chain has developed a new set of challenges for security researchers. Among them, malicious alterations of hardware designs at an untrusted facility, or Trojan insertion, are considered one of the most difficult challenges. While side-channel analysis-based hardware Trojan detection techniques have shown great potential, most solutions, proposed over the past decade, require the availability of golden (i.e., Trojan-free) chips and are susceptible to process variations. Few techniques that do not require a golden chip depend on simulation-based modeling of the side-channel signature, which may not be reliable for differentiating between process and Trojan induced variations. Furthermore, most of these techniques are evaluated either using very few Trojan inserted chips or simulation-based test setup. Spatial and temporal self-referencing-based detection mechanisms proposed earlier effectively eliminate the need for a golden chip and the impact of process variations. However, these techniques have not been adequately studied to achieve high detection sensitivity. In this article, we propose a golden-free multidimensional self-referencing technique that analyzes the side-channel signatures in both the time and frequency domains to significantly broaden the Trojan coverage and strengthen the detection confidence. We introduce a fully automated detection framework containing systematic methodologies for test generation, signature extraction, signal processing, threshold calculation, and metric-based decision-making that effectively enables the synergistic self-referencing approach. Finally, we evaluate the proposed technique through a comprehensive hardware measurement setup consisting of 96 Trojan-inserted test chips. Along with achieving a high detection coverage, we demonstrate that the analysis of spatial and temporal discrepancies in both frequency and time domains helps to reliably detect small hard-to-detect Trojans under process and measurement induced variations.

Hardware Trojan Detection at Behavioral Level Using Inline Assertions and Verification Using UVM

Abstract: Recently, hardware Trojan (HT) is posing a significant challenge to the integrated circuit (IC) industry and has inspired various improvements in the Trojan identification plans. This research study presents the inline assertions for the detection of hardware Trojan at the behavioral level of a system on chip (SoC). In the proposed RTL design, a modified circuit design flow is suggested to incorporate inline assertions into a SoC. Flexible inline assertions are developed in the RTL block within the design module. The router IP design and inline assertions are synthesized and implemented in Xilinx Vivado and Aldec Rivera Pro using Verilog HDL. The universal verification methodology (UVM) is also used to verify the proposed design with the different test case scenarios. The functional coverage and code coverage are analyzed in Aldec Rivera Pro. Parameters such as power and area are analyzed in the Synopsys design compiler (DC).

Hardware Trojan Detection Using Unsupervised Deep Learning on Quantum Diamond Microscope Magnetic Field Images

Abstract: This article presents a method for hardware trojan detection in integrated circuits. Unsupervised deep learning is used to classify wide field-of-view (4 × 4 mm2), high spatial resolution magnetic field images taken using a Quantum Diamond Microscope (QDM). QDM magnetic imaging is enhanced using quantum control techniques and improved diamond material to increase magnetic field sensitivity by a factor of 4 and measurement speed by a factor of 16 over previous demonstrations. These upgrades facilitate the first demonstration of QDM magnetic field measurement for hardware trojan detection. Unsupervised convolutional neural networks and clustering are used to infer trojan presence from unlabeled data sets of 600 × 600 pixel magnetic field images without human bias. This analysis is shown to be more accurate than principal component analysis for distinguishing between field programmable gate arrays configured with trojan-free and trojan-inserted logic. This framework is tested on a set of scalable trojans that we developed and measured with the QDM. Scalable and TrustHub trojans are detectable down to a minimum trojan trigger size of 0.5% of the total logic. The trojan detection framework can be used for golden-chip-free detection, since knowledge of the chips’ identities is only used to evaluate detection accuracy.

A Survey on Hardware Vulnerability Analysis Using Machine Learning

Abstract: Electronic systems rely on efficient hardware, popularly known as system-on-chip (SoC), to support its core functionalities. A typical SoC consists of diverse components gathered from third-party vendors to reduce SoC design cost and meet time-to-market constraints. Unfortunately, the participation of third-party companies in global supply chain introduces potential security vulnerabilities. There is a critical need to efficiently detect and mitigate hardware vulnerabilities. Machine learning has been successfully used in hardware security verification as well as development of effective countermeasures. There are recent surveys on hardware Trojan detection using machine learning. To the best of our knowledge, there are no comprehensive surveys on utilization of machine learning techniques for detection and mitigation of a wide variety of hardware vulnerabilities including malicious implants (e.g., hardware Trojans), side-channel leakage, reverse engineering, and supply-chain vulnerabilities (e.g., counterfeiting, overbuilding and recycling). In this paper, we provide a comprehensive survey of hardware vulnerability analysis using machine learning techniques. Specifically, we discuss how existing approaches effectively utilize machine learning algorithms for hardware security verification using simulation-based validation, formal verification as well as side-channel analysis.

Golden Reference-Free Hardware Trojan Localization Using Graph Convolutional Network

Abstract: The globalization of the integrated circuit (IC) supply chain has moved most of the design, fabrication, and testing process from a single trusted entity to various untrusted third-party entities worldwide. The risk of using untrusted third-Party Intellectual Property (3PIP) is the possibility for adversaries to insert malicious modifications known as Hardware Trojans (HTs). These HTs can compromise the integrity, deteriorate the performance, deny the service, and alter the functionality of the design. While numerous HT detection methods have been proposed in the literature, the crucial task of HT localization is overlooked. Moreover, a few existing HT localization methods have several weaknesses: reliance on a golden reference, inability to generalize for all types of HT, lack of scalability, low localization resolution, and manual feature engineering/property definition. To overcome their shortcomings, we propose a novel, golden reference-free HT localization method at the pre-silicon stage by leveraging graph convolutional network (GCN). In this work, we convert the circuit design into its intrinsic data structure, graph, and extract the node attributes. Afterward, the graph convolution performs automatic feature extraction for nodes to classify the nodes as Trojan or benign. Our approach is automated and does not burden the designer with manual code review. It locates the Trojan signals with 99.6% accuracy, 93.1% $F1$ -score, and a false-positive rate below 0.009%.

A Novel Algorithm for Hardware Trojan Detection Through Reverse Engineering

Abstract: Malicious alteration in an IC design is generally referred to as hardware Trojans (HTs). The involvement of multiple entities in the VLSI design cycle has made the process of HT detection very challenging. This article presents a novel method for the detection of HT at the gate level of abstraction. A path retrace algorithm detects the nets added/deleted by an adversary along with its location. The netlists of the genuine circuit (design netlist) and the Trojan-inserted circuit are used by the algorithm to detect the malicious nets in the circuit. This method utilizes testability analysis as the metric for segregating malicious nets in the compromised circuit netlist. Netlist of the fabricated IC, which is obtained through reverse engineering and the design netlist of the original circuit are used to determine the testability parameters, such as controllability and observability of the nets. Based on the variation in testability metrics of a signal in the original circuit, the path retrace algorithm identifies the malicious gates inserted into the original circuit. In addition, the algorithm also helps to isolate the Trojan circuit and comprehend its functional implication on the original design. Using the list of malicious gates and compromised circuit netlist, it is possible to identify the Trojan nets inserted by the adversary. This technique is more effective in detecting functional Trojans as compared to techniques employing reverse engineered images as it is design parameter independent and impervious to noise.

AdaTest: Reinforcement Learning and Adaptive Sampling for On-chip Hardware Trojan Detection

Abstract: This paper proposes AdaTest, a novel adaptive test pattern generation framework for efficient and reliable Hardware Trojan (HT) detection. HT is a backdoor attack that tampers with the design of victim integrated circuits (ICs). AdaTest improves the existing HT detection techniques in terms of scalability and accuracy of detecting smaller Trojans in the presence of noise and variations. To achieve high trigger coverage, AdaTest leverages Reinforcement Learning (RL) to produce a diverse set of test inputs. Particularly, we progressively generate test vectors with high ‘reward’ values in an iterative manner. In each iteration, the test set is evaluated and adaptively expanded as needed. Furthermore, AdaTest integrates adaptive sampling to prioritize test samples that provide more information for HT detection, thus reducing the number of samples while improving the samples’ quality for faster exploration. We develop AdaTest with a Software/Hardware co-design principle and provide an optimized on-chip architecture solution. AdaTest’s architecture minimizes the hardware overhead in two ways: (i) Deploying circuit emulation on programmable hardware to accelerate reward evaluation of the test input; (ii) Pipelining each computation stage in AdaTest by automatically constructing auxiliary circuit for test input generation, reward evaluation, and adaptive sampling. We evaluate AdaTest’s performance on various HT benchmarks and compare it with two prior works that use logic testing for HT detection. Experimental results show that AdaTest engenders up to two orders of test generation speedup and two orders of test set size reduction compared to the prior works while achieving the same level or higher Trojan detection rate.

An Efficient Framework with Node Filtering and Load Expansion for Machine-Learning-Based Hardware Trojan Detection

Abstract: The globalization of the integrated circuit (IC) industry has raised concerns about hardware Trojans (HT), and there is an urgent need for efficient HT-detection methods of gate-level netlists. Machine learning (ML) is a powerful tool for this purpose. A Trojan-detection framework is proposed in this paper to solve the data imbalance and low accuracy problems of existing ML-based HT-detection algorithms. To solve the problem of data imbalance, we propose the node-filtering algorithm, which extracts structure templates from HT circuits and removes most normal nodes based on them. To enhance the identification of unknown HT payload, we propose the load-expansion algorithm, which expands the identified HT nodes based on their fanout features. We evaluate the framework using different ML algorithms. The results show that the framework significantly improves the Trojan-detection rate of the original algorithms, and achieves a 10% improvement in true positive rate compared to the original algorithms.

Fortified-NoC: A Robust Approach for Trojan-Resilient Network-on-Chips to Fortify Multicore-Based Consumer Electronics

Abstract: Consumer electronics hardware is designed and manufactured following a global supply chain which opens doors to their security challenges. Even with the advanced methods of formal verification and coverage analysis, there is still a chance of hiding malicious hardware/software which can degrade performance, leak data, or even stop functionalities. In this work, we present security solution of Network on Chip (NoC) based Multiprocessor System-on-Chip (MPSoC) consumer electronics (CE) systems such as set-top boxes and autonomous vehicles. Most of the existing methods targeted for such systems focus on protection in Network Interfaces (NI) and other software solutions rather than routers against Hardware Trojans (HT) which can be embedded in NoC by a rogue designer. In this work, we propose a 3-tier methodology leading to “Fortified-NoC” to secure the data and resources against different kinds of threats. A Trojan cognizant routing algorithm (TCRA) is proposed which limits the HTs to a particular router that contains them. Data shuffling with Trojan detectability is also used to mislead and identify the HTs. We validated the proposed approach using various experiments. Our proposed method is capable of mitigating the Trojan attacks such as data leakage, performance degradation, denial of service and live locking of data packets at the cost of a little latency and, some extra hardware. It is able to recover more than 80% of lost packets, improve the throughput by $1.3\times $ against performance degrading Trojan attacks.

A Hardware Trojan Detection and Diagnosis Method for Gate-Level Netlists Based on Different Machine Learning Algorithms

Abstract: The design complexity and outsourcing trend of modern integrated circuits (ICs) have increased the chance for adversaries to implant hardware Trojans (HTs) in the development process. To effectively defend against this hardware-based security threat, many solutions have been reported in the literature, including dynamic and static techniques. However, there is still a lack of methods that can simultaneously detect and diagnose HT circuits with high accuracy and low time complexity. Therefore, to overcome these limitations, this paper presents an HT detection and diagnosis method for gate-level netlists (GLNs) based on different machine learning (ML) algorithms. Given a GLN, the proposed method first partitions it into several circuit cones and extracts seven HT-related features from each cone. Then, we repeat this process for the sample GLN to construct a dataset for the next step. After that, we use K-Nearest Neighbor (KNN), Decision Tree (DT) and Naive Bayes (NB) to classify all circuit cones of the target GLN. Finally, we determine whether each circuit cone is HT-implanted through the label, completing the HT detection and diagnosis for target GLN. We have applied our method to 11 GLNs from ISCAS’85 and ISCAS’89 benchmark suites. As shown in experimental results of the three ML algorithms used in our method: (1) NB costs shortest time and achieves the highest average true positive rate (ATPR) of 100%; (2) DT costs longest time but achieve the highest average true negative rate (ATNR) of 98.61%; (3) Compared to NB and DT, KNN costs a slightly longer time than NB but the ATPR and ATNR values are approximately close to DT. Moreover, it can also report the possible implantation location of a Trojan instance according to the detecting results.

Deep Learning-Based Hardware Trojan Detection With Block-Based Netlist Information Extraction

Abstract: With the globalization of the semiconductor industry, hardware Trojans (HTs) are an emergent security threat in modern integrated circuit (IC) production. Research is now being conducted into designing more accurate and efficient methods to detect HTs. Recently, a number of machine learning (ML)-based HT detection approaches have been proposed; however, most of them still use knowledge-driven approaches to design features and often use engineering intuition to carefully craft the detection model to improve accuracy. Therefore, in this work, we propose a data-driven HT detection system based on gate-level netlists. The system consists of four main parts: 1) Information extraction from netlist block; 2) Natural language processing (NLP) for translating netlist information; 3) Deel learning (DL)-based HT detection model; 4) HT component final voter. In the experiments, both a long short-term memory networks (LSTM) model and convolutional neural network (CNN) model are used as our detection models. We performed the experiments on the HT benchmarks from Trust-hub and K-fold crossing verification has been applied to evaluate different parameter settings in the training procedure. The experimental results show that the proposed HT detection system can achieve 79.29% TPR, 99.97% TNR, 87.75% PPV and 99.94% NPV for combinational Trojan detection and 93.46% TPR, 99.99% TNR, 98.92% PPV and 99.92% NPV for sequential Trojan detection after voting-based optimization using the LEDA library-based HT benchmarks ( logic_level =4, upsampling, LSTM, 5 epochs).

Securing Hardware Development Process using Blockchain

Abstract: Modern microprocessors contain millions of gates and finding a small hidden malicious hardware trojan (HT) is difficult. Additionally, these HTs may not need any additional external input pins to activate. Many solutions have been proposed to find these HTs, but none of the solutions gives promising result due to their limitations. Moreover, pre-silicon verification and post-silicon testing also don't address the issue of HTs. In this paper we present methodology to limit the possibily of inserting HTs based on blockchain technology. It is better to limit the opportunity for insertion of HT than finding them afterwards in the design and fabrication process. We proposed a solution for monitoring hardware development process files to maintain integrity and trustful relationship using encryption and smart contracts in a blockchain network.

Design of AI Trojans for Evading Machine Learning-based Detection of Hardware Trojans

Abstract: The globalized semiconductor supply chain significantly increases the risk of exposing System-on-Chip (SoC) designs to malicious implants, popularly known as hardware Trojans. Traditional simulation-based validation is unsuitable for detection of carefully-crafted hardware Trojans with extremely rare trigger conditions. While machine learning (ML) based Trojan detection approaches are promising due to their scalability as well as detection accuracy, ML-based methods themselves are vulnerable from Trojan attacks. In this paper, we propose a robust backdoor attack on ML-based Trojan detection algorithms to demonstrate this serious vulnerability. The proposed framework is able to design an AI Trojan and implant it inside the ML model that can be triggered by specific inputs. Experimental results demonstrate that the proposed AI Trojans can bypass state-of-the-art defense algorithms. Moreover, our approach provides a fast and cost-effective solution in achieving 100% attack success rate that significantly outperforms state-of-the art approaches based on adversarial attacks.

A security method of hardware Trojan detection using path tracking algorithm

Abstract: Abstract Recently, the issue of malicious circuit alteration and attack draws more attention than ever before due to the globalization of IC design and manufacturing. Malicious circuits, also known as hardware Trojans, are found able to degrade the circuit performance or even leak confidential information, and accordingly it is definitely an issue of immediate concern to develop detection techniques against hardware Trojans. This paper presents a ring oscillator-based detection technique to improve the hardware Trojan detection performance. A circuit under test is divided into a great number of blocks, path assignment is optimized using a path tracking algorithm, and a high coverage is reached accordingly.

Run-Time Hardware Trojan Detection in Analog and Mixed-Signal ICs

Abstract: Hardware Trojan (HT) insertion is a major security threat for electronic components that demand a high trust level. Several HT attack mechanisms have been demonstrated to date, and several HT prevention and detection countermeasures have been proposed to thwart HT attacks. Given the multitude of HT attack mechanisms, run-time monitors for HT detection are used as a last line of defense. In this paper, we propose a run-time monitoring methodology for HT attack mechanisms affecting the analog and mixed-signal (AMS) sections of an Integrated Circuit (IC). The methodology is based on the Symmetry-based Built-In Self-Test (SymBIST) principle that relies on distributing invariances across the IC and continuously checking for their compliance. Detection of various HT attacks are demonstrated on a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) IP at transistor-level.

Hardware obfuscation of AES IP core using combinational hardware Trojan circuit for secure data transmission in IoT applications

Abstract: In semiconductor industry, reusability‐based System‐on‐Chip architecture using hardware intellectual property (IP) cores play a prominent role in Internet‐of‐Things (IoT) applications for secure data transmission. The advent of IoT makes it possible for physical things to transmit, process, compute, and receive data over internet. But, it also introduces in‐device communication security vulnerabilities. Advanced Encryption Standard (AES) IP has been used to address security vulnerabilities in IoT. It is an efficient and high‐performance crypto algorithm used in IoT devices for secure and fast data encryption. However, due to rise of many attacks, the security of AES IP is also under threat. Hardware obfuscation is one such prominent countermeasure that mitigates hardware attacks such as tampering, reverse engineering, and malicious alteration. This article presents secure AES IP mechanism using the potential technique of obfuscation inspired by the concept of combinational hardware Trojan. Experimental results show that the proposed technique is resilient against reverse‐engineering, malicious alteration, Boolean satisfiability attack, and key‐sensitizing attacks. The confusion and diffusion features of obfuscated AES IP are higher in terms of Hamming distance, avalanche effect, and balance rate. The proposed technique is implemented in Basys‐3 FPGAs within 5% of power and area overhead while maintaining high throughput.

A security method of hardware Trojan detection using path tracking algorithm

Abstract: Abstract Recently, the issue of malicious circuit alteration and attack draws more attention than ever before due to the globalization of IC design and manufacturing. Malicious circuits, also known as hardware Trojans, are found able to degrade the circuit performance or even leak confidential information, and accordingly it is definitely an issue of immediate concern to develop detection techniques against hardware Trojans. This paper presents a ring oscillator-based detection technique to improve the hardware Trojan detection performance. A circuit under test is divided into a great number of blocks, path assignment is optimized using a path tracking algorithm, and a high coverage is reached accordingly.

Electromagnetic Side-Channel Hardware Trojan Detection Based on Transfer Learning

Abstract: Hardware Trojan detection method has been given particular attentions by hardware security researchers since the failure of Syrian radars in 2007. Electromagnetic side-channel analysis is a promising method which is widely used in practice due to its advantage of efficiency, non-touch and high accuracy. In this brief, we propose a novel method using electromagnetic side-channel signal for hardware Trojan detection by transfer learning. Firstly, time-frequency information of electromagnetic signal is extracted by continuous wavelet transform to take full advantage of useful information in time domain and frequency domain. Then, time-frequency information is fed to transfer learning network to get the classification result. In order to further improve the result, we use transfer learning to further extract the key features in time-frequency information. Finally, the key features are classified by the support vector machine to improve the accuracy. The experiment is conducted on a stand FPGA board and advanced encryption standard circuit is used as the benchmark circuit. Experimental results show that our methods can improve the result efficiently.

Golden Model-Free Hardware Trojan Detection by Classification of Netlist Module Graphs

Abstract: In a world where increasingly complex integrated circuits are manufactured in supply chains across the globe, hardware Trojans are an omnipresent threat. State-of-the-art methods for Trojan detection often require a golden model of the device under test. Other methods that operate on the netlist without a golden model cannot handle complex designs and operate on Trojan-specific sets of netlist graph features. In this work, we propose a novel machine-learning-based method for hardware Trojan detection. Our method first uses a library of known malicious and benign modules in hierarchical designs to train an eXtreme Gradient Boosted Tree Classifier (XGBClassifier). For training, we generate netlist graphs of each hierarchical module and calculate feature vectors comprising structural characteristics of these graphs. After the training phase, we can analyze the synthesized hierarchical modules of an unknown design under test. The method calculates a feature vector for each module. With this feature vector, each module can be classified into either benign or malicious by the previously trained XGBClassifier. After classifying all modules, we derive a classification for all standard cells in the design under test. This technique allows the identification of hardware Trojan cells in a design and highlights regions of interest to direct further reverse engineering efforts. Experiments show that this approach performs with >97 % Sensitivity and Specificity across available and newly generated hardware Trojan benchmarks and can be applied to more complex designs than previous netlist-based methods while maintaining similar computational complexity.

Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits

Abstract: With Cyber warfare, detection of hardware Trojans, malicious digital circuit components that can leak data and degrade performance, is an urgent issue. Quasi-Delay Insensitive asynchronous digital circuits, such as NULL Convention Logic (NCL) and Sleep Convention Logic, also known as Multi-Threshold NULL Convention Logic (MTNCL), have inherent security properties and resilience to large fluctuations in temperatures, which make them very alluring to extreme environment applications, such as space exploration, automotive, power industry etc. This paper shows how dual-rail encoding used in NCL and MTNCL can be exploited to design Trojans, which would not be detected using existing methods. Generic threat models for Trojans are given. Formal verification methods that are capable of accurate detection of Trojans at the Register-Transfer-Level are also provided. The detection methods were tested by embedding Trojans in NCL and MTNCL Rivest-Shamir-Adleman (RSA) decryption circuits. The methods were applied to 25 NCL and 25 MTNCL RSA benchmarks of various data path width and provided 100% rate of detection.

A PCA Based SVM Hardware Trojan Detection Approach

Abstract: In recent years, with the globalization of semiconductor processing and manufacturing, integrated circuits have gradually become vulnerable to malicious attackers. In order to detect Hardware Trojans (HTs) hidden in integrated circuits, it has become one of the hottest issues in the field of hardware security. In this paper, we propose to apply Principal Component Analysis (PCA) and Support Vector Machine (SVM) to hardware Trojan detection, using PCA algorithm to extract features from small differences in side channel information, and then obtain the principal components. The SVM detection model is optimized by means of cross-validation and logarithmic interval. Finally, it is determined whether the original circuit contains a hardware Trojan. In the experiment, we use the SAKURA-G FPGA board, Agilent oscilloscope, and ISE simulation software to complete the experimental work. The test results of five different HTs show that the average True Positive Rate (TPR) of the proposed method for HTs can reach 99.48%, along with an average True Negative Rate (TNR) of 99.2%, and an average detection time of 9.66s.

A novel hardware Trojan detection method based on sweep‐frequency test

Abstract: This paper proposes a novel hardware Trojan detection method based on sweep-frequency test since Trojan horse threatens information security seriously. An equivalent parasitic and load circuit model, and analysis method are depicted in detail. Experimental results of the amplitude-frequency responses between the input and output accord with the simulation results. 11 golden chips and 9 Trojan chips are used for the sweep-frequency tests, and the golden chips can be distinguished from Trojan chips accurately based on the relationship between the peak and valley resonant frequencies, which indicates that the proposed model and detection method are effective.