Showing papers on "Junction temperature published in 2003"

Reducing power density through activity migration

Abstract: Power dissipation is unevenly distributed in modern microprocessors leading to localized hot spots with significantly greater die temperature than surrounding cooler regions Excessive junction temperature reduces reliability and can lead to catastrophic failure We examine the use of activity migration which reduces peak junction temperature by moving computation between multiple replicated units Using a thermal model that includes the temperature dependence of leakage power, we show that sustainable power dissipation can be increased by nearly a factor of two for a given junction temperature limit Alternatively, peak die temperature can be reduced by 124/spl deg/C at the same clock frequency The model predicts that migration intervals of around 20-200 /spl mu/s are required to achieve the maximum sustainable power increase We evaluate several different forms of replication and migration policy control

Active thermal control of power electronics modules

Abstract: Active thermal control techniques make it feasible to regulate the steady state and transient thermal-mechanical stress in power electronic modules for applications such as motor drives. Online junction temperature estimation and manipulation of the switching frequency and current limit to regulate the losses are used to prevent overtemperature and power cycling failures in insulated gate bipolar transistor (IGBT) power modules. The techniques developed in this work are used to actively control the junction temperature of the power module. This control strategy improves power module reliability and increases utilization of the silicon thermal capacity by providing sustained operation at maximum attainable performance limits.

Adaptive temperature dependent feedback clock control system and method

Abstract: An adaptive temperature dependent clock feedback control system and method for adaptively varying a frequency of a clock signal to a circuit such that the circuit may operate at a maximum safe operating clock frequency based on a circuit junction temperature. The clock control system includes a thermal sensor and a temperature dependent dynamic overclock generator circuit. The thermal sensor detects a junction temperature corresponding to at least a portion of the circuit on a semiconductor die. The temperature dependent dynamic overclock generator circuit varies the clock signal based on the semiconductor die junction temperature, such that the clock signal operates at the highest possible operating frequency associated with the detected junction temperature. The frequency of the clock signal is increased from a first frequency to at least a second frequency and a third frequency if the junction temperature is below a lower junction temperature threshold.

LED junction temperature tester

Abstract: An instrument measures the LED junction temperature directly by taking advantage of the linear relationship between the forward current driven through the LED, the forward drop of the LED, and the junction temperature to determine the LED junction temperature Calibration is conducted by placing two LEDs from the same family in ambient temperature and passing a small test current through each of the LEDs to obtain the forward drop of the LED at ambient temperature The LED under test is then placed in an environmentally-controlled chamber where the temperature is raised a known amount above ambient temperature Known low and high voltage values are associated with the ambient temperature and the environmental chamber temperature, causing the LED under test becomes a calibrated thermometer that can measure its own junction temperature due to the linear relationship between the forward drop and the junction temperature

A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management

Abstract: Accurate estimation of the silicon junction (or die) temperature in high-end microprocessors is crucial for various performance analyses and also for chip-level thermal management This work introduces for the first time, the notion of self-consistency in estimating the die temperature for sub-100 nm CMOS technologies by taking into account various electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature It also comprehends chip-level reliability constraints and the impact of employing various packaging and cooling solutions in an integrated manner The self-consistent solutions of die temperature are shown to have significant implications for evaluating various power-performance-reliability-cooling cost tradeoffs and can be used to optimize the performance of nanoscale ICs

An effective methodology for thermal characterization of electronic packaging

Abstract: An effective and novel methodology that integrates infrared (IR) thermography measurement and a three-dimensional (3-D) finite element (FE) model is proposed for thermal characterization of packages in a steady state under a natural convection environment based on JEDEC specification . To perform surface temperature measurement using an IR thermometer, a black paint coating is applied on the surface of packages so as to calibrate the surface radiation. The associated emissivity is approximately assessed using a simple calibration experiment, and an appropriate thickness of the coating is determined. By using a typical 100-lead Thin Quad Flat package (TQFP) as the test vehicle, the proposed methodology is benchmarked by a thermal test die measurement in terms of the junction-to-ambient (J/A) thermal resistance and the chip junction temperature. To demonstrate the accuracy of the benchmarked data from the thermal test die measurement, a corresponding uncertainty analysis is performed. It is found that the worst possible uncertainty in the measured power, based on the specific power supply, is about 0.005 W and that of chip junction temperature measurement is about 0.78/spl deg/C. Additional studies are performed to evaluate the feasibility of the correlation models for convective heat transfer coefficients on typical TQFP packages. It turns out that for a small device such as the TQFP package, these correlation models are fairly reliable.

Air-cooling extension - performance limits for processor cooling applications

Abstract: The last two decades have seen a steady increase in microprocessor performance as silicon technology continues to scale in accordance with Moore's law. This increasing performance of the microprocessors is also associated with an increase in thermal design power and an increase in both average power density and local power density, commonly referred to as "hot spots". The thermal solutions must ensure that the junction temperature of the processor (die temperature) does not exceed temperatures in the 90-110/spl deg/C range, typically at the hot spots, to ensure device performance and reliability. The majority of OEMs (original equipment manufacturers) within the microelectronics industry would like to achieve this by extending the application of air-cooling technologies. The objectives of this paper are: 1) to present the air-cooling extension for a range of "reasonable" boundary conditions; and 2) to introduce some novel technologies, which may substantially extend the air-cooling applications.

Evaluation of 1200 V-Si-IGBTs and 1300 V-SiC-JFETs for application in three-phase very sparse matrix AC-AC converter systems

Abstract: In this paper based on experimental investigations of the power semiconductor switching behavior and on analytical calculations the conduction and switching losses of it three-phase very sparse AC-AC matrix converter (VSMC) supplying a permanent magnet synchronous motor are discussed in detail. There, 1200 V-Si-IGBTs/1200 V-Si-ultra-fast-recovery diodes and 1300 V-SiC-JFET/Si-MOSFET cascodes are employed for realizing the converter power circuit. The worst case operating conditions are identified and the efficiencies resulting in dependency of the switching frequency and load current amplitude are shown in graphical form. Furthermore, the operating range of the VSMC with respect to the maximum admissible junction temperature of the power semiconductors is determined. Finally, topics to be treated in the continuation of the research are discussed briefly.

Integrating giant magnetoresistive current and thermal sensors in power electronic modules

Abstract: Motor drive technology relies on power electronic devices and current sensors for motor control. With active thermal control of IGBT junction temperatures, the reliability and full utilization of power devices can be improved. The intent of this research is to introduce the module-level integration of the GMR field detector as both a current and temperature sensor. The integration effort also includes a new type of flexible planar interconnect to replace conventional wire bonds. The integration goal is to improve the reliability and lower the cost of motor drive systems. Cost and reliability will benefit from a lower parts count and fewer interconnections. Because of the small size, inherent galvanic isolation, temperature dependence, high sensitivity and bandwidth, the magnetoresistive field detector offers promising options for both integrated current and temperature sensing methods. This research describes the operation of GMR, as well as the necessary signal conditioning circuitry for integrated current and temperature sensing. The measured performance attributes of the sensor are also shown. Finally, future plans are discussed which involve combining the current and temperature sensing capabilities with the design of an interconnect layout and observers for junction temperature estimation.

A practical method to extract the thermal resistance for heterojunction bipolar transistors

Abstract: Self-heating of bipolar transistors can lead to a significant increase of their junction temperature This must be correctly considered for accurate modeling and also to ensure reliability Because of this, several measurement techniques for thermal resistance extraction were proposed in the literature However, a drawback of most methods is that they require measurements at different ambient temperatures for each device This is very tedious if a large number of different transistors must be investigated Therefore, we present a new technique that allows extraction of the thermal resistance from simple measurements carried out at only one ambient temperature, based on previously determined technology-specific data Moreover, as a byproduct, the emitter resistance is estimated The validity of this method is demonstrated here for SiGe HBTs, but it has also been used successfully for GaAs HBTs

Method and apparatus for estimating semiconductor junction temperature

Abstract: An apparatus is disclosed that provides an estimate of the semiconductor junction temperature of a semiconductor device as a function of the electrical current flowing across the corresponding semiconductor junction. The apparatus includes a current sensor that samples and measures the current flowing across the semiconductor junction and provides an output signal indicative of the measured value to a current-to-temperature converter. The current-to-temperature converter estimates the temperature of the semiconductor junction using equations that include constants empirically derived for the particular device configuration including cooling and mounting methods used with it. The current-to-temperature converter provides an output temperature signal that is compared to a predetermined temperature threshold value, and in the event that the output temperature signal exceeds the predetermined temperature threshold value, an alarm signal is set.

Effect of CMOS technology scaling on thermal management during burn-in

Abstract: Burn-in is a quality improvement procedure challenged by the high leakage currents that are rapidly increasing with IC technology scaling. These currents are expected to increase even more under the new burn-in environments leading to higher junction temperatures, possible thermal runaway, and yield loss during burn-in. The authors estimate the increase in junction temperature with technology scaling. Their research shows that under normal operating conditions, the junction temperature is increasing 1.45/spl times//generation. The increase in junction temperature under the burn-in condition was found to be exponential. The range of optimal burn-in voltage and temperature is reduced significantly with technology scaling.

Teaching thermal design of power electronic systems with web-based interactive educational software

Abstract: For designing reliable power electronic systems it is essential to understand basic thermal issues like the stationary and transient relation of the power semiconductor losses the junction temperature and the application of thermal equivalent circuits. Also, thermal properties are of special importance in connection with further increasing the compactness of power converter systems. The aim of this paper is to give an introduction into the basic theory of heat energy conduction and thermal design which should serve as an addition to the Java applets compiled in a the iPES-Thermal, a module of the interactive educational software iPES which is freely available at www.ipes.ethz.ch and employed at the ETH Zurich for supporting an introductory course on power electronics.

Burn-in temperature projections for deep sub-micron technologies

Abstract: Burn-in faces significant challenges in recent CMOS technologies. The self-generated heat of each IC in a burn-in environment contributes to larger currents that can lead to further increase in junction temperatures, possible thermal run away, and yield-loss of good parts. Calculations show that the junction temperature is increasing by 1.45X/generation. This paper estimates the increase in junction temperature with scaling and discusses the optimal burn-in temperature with scaling. Our research indicates that the burn-in temperature must also be reduced with technology scaling. The impact on commercial burn-in ovens is also described.

Numerical prediction of electronic component heat transfer: an industry perspective

Abstract: This study aims to provide a perspective on the current capabilities of computational fluids dynamics (CFD) as a design tool to predict component operating temperature in electronic systems. A systematic assessment of predictive accuracy is presented for printed circuit board (PCB) mounted component heat transfer, using a CFD code dedicated to the thermal analysis of electronic systems. Component operating temperature predictive accuracy ranges from +3/spl deg/C to +22/spl deg/C (up to 35%) of measurement, depending on component location on the board, airflow velocity and flow model applied. Combined with previous studies, the results highlight that component junction temperature needs to be experimentally measured when used for strategic product design decisions and reliability predictions. Potential development areas are discussed for improved analysis.

Large time-scale electro-thermal simulation for loss and thermal management of power MOSFET

Abstract: In power electronics systems the management of power loss and temperature of switching devices is indispensable for the reliability of the whole system. In this paper, a simple electro-thermal simulation model is presented. This simulation model is capable of predicting the power loss and estimating the junction temperature of power device in various environmental conditions. The electro-thermal model is composed of electrical network model, semiconductor device model and thermal network model. These parts interact with each other to calculate the loss and temperature of device and parameters of each model. By focusing on the slow dynamics of heat sink temperature, the proposed model can be employed for the large time-scale simulations. A 200 W boost converter using a power MOSFET as an active switch and adopting a natural convection cooling aluminum heat sink as a cooling device was taken as an example system. The experimental results are compared with the predicted values of the simulation model.

Impact of junction temperature on microelectronic device reliability and considerations for space applications

Abstract: The space community and other high reliability users of microelectronic devices have been derating junction temperature and other critical stress parameters for decades to improve device reliability and extend operating life. Semiconductor technology scaling and process improvements, however, compel us to reassess common failure mechanisms and established derating guidelines to provide affirmation that common derating factors remain adequate for current technologies used in high reliability space applications. It is incumbent upon the user to develop an understanding of advanced technology failure mechanisms through modeling, accelerated testing, and failure analysis prior to product insertion in critical applications. This paper provides a summary of an industry survey on junction temperature derating from key microelectronics suppliers, and offers recommendations to users for temperature derating for reliable operation over time. Background information on established derating factors, and recommendations for safe operating junction temperatures for newer technologies are also presented.

A silicon-carbide micro-capillary pumped loop for cooling high power devices

Abstract: As more high-power wide-bandgap devices are being utilized, the thermal management issues associated with these devices need to be resolved. High power devices dissipate excessive heat that must be cooled, but traditional cooling methods are insufficient to provide such a cooling means. Although using SiC allows higher operating temperatures, an upper temperature threshold still exists for high frequency devices. The package under study consists of a SiC high frequency power device whose junction temperature must not exceed a specified temperature, such as 150/spl deg/C, 175/spl deg/C, or 200/spl deg/C, set by the particular device technology. The technical goal is to develop an innovative cooling concept providing less than 100/spl deg/C temperature rise relative to the base plate. In the baseline configuration, a high power SiC device is mounted onto a shim or thermal spacer that is then mounted onto a cold plate. This paper evaluates a SiC microcapillary pumped loop thermal management system that is incorporated into the shim of the device, taking advantage of phase-change to increase the thermal conductivity of the system. The results of the modeling, fabrication, and testing of the thermal management system are discussed.

Thermal solutions for discrete and wafer-level RF MEMS switch packages

Abstract: In discrete radio frequency (RF) microelectromechanical systems (MEMS) packages, MEMS devices were fabricated on silicon or gallium arsenide (GaAs) chips. The chips were then attached to substrates with die attach materials. In wafer-level MEMS packages, the switches were manufactured directly on substrates. For both types of packages, when the switches close, a contact resistance of approximately 1 /spl Omega/ exists at the contact area. As a result, during switch operations, a considerable amount of heat is generated in the minuscule contact area. The power density at the contact area could be up to 1000 times higher than that of typical power amplifiers. The high power density may overheat the contact area, therefore affect switch performance and jeopardize long-term switch reliabilities. In this paper, thermal analysis has been performed to study the heat dissipation at the switch contact area. The goal is to control the "hot spots" and lower the maximum junction temperature at the contact area. A variety of chip materials, including Silicon, GaAs have been evaluated for the discrete packages. For each chip material, the effect of die attach materials has been considered. For the wafer-level packages, various substrate materials, such as ceramic, glass, and low-temperature cofired ceramic (LTCC) have been studied. Thermal experiments have been conducted to measure the temperature at the contact area and its vicinity as a function of dc and RF powers. Several solutions in material selection and package configurations have been explored to enable the use of MEMS with chips or substrates with relatively poor thermal conductivity. For discrete MEMS packages, placing the die inside a copper cavity on the substrate provides significant heat dissipation. For wafer-level packages, thin diamond coatings on the substrate could reduce the hot-spot temperature considerably.

Thermal management of high performance microprocessors in burn-in environment

Abstract: In deep sub-micron CMOS technologies, increased standby current in high performance processors results in increased junction temperature. This elevated temperature has a positive feedback on the standby current. If the temperature is not controlled, it may lead to thermal runaway. In this paper we investigate the thermal management of high performance chips in the burn-in environment.

Temperature controller and array waveguide lattice type optical wavelength multiplexer/demultiplexer

Abstract: In a temperature control device which maintains an object to be controlled at a preset constant temperature and an arrayed waveguide grating optical wavelength multiplexer/demultiplexer, the adverse effect of the junction temperature of the semiconductor control element is eliminated for the purpose of simplifying the overall structure and improving operation efficiency sufficiently without any trouble. The object 10 to be controlled, which is an arrayed waveguide grating optical wavelength multiplexing/demultiplexing element, is fixed on the soaking plate 2 which is made from a good heat conductive material. The semiconductor control element 3 with a control terminal which functions as a heat generator by using its-junction temperature and a temperature sensor 5 are fixed on the soaking plate 2. A negative feedback control is applied to the conduction condition of the semiconductor control element 3 in accordance with the error signal s3 which indicates the difference between the present temperature signal s2 obtained from the temperature detection signal s4 transmitted from the temperature sensor 5 and the preset target temperature signal s1. Consequently, the junction temperature of the semiconductor control element 3 is effectively used as a heating source not as a loss, thereby reducing the power consumption and stabilizing the performance.

Advanced thin wafer IGBTs with new thermal management solution

Abstract: This paper presents the new design concepts for improving the short-circuit capability of thin wafer power devices, such as field-stop (FS) IGBTs, by thermal management techniques. The experimental results of thin wafer IGBTs, with lead-frame connection via solid copper emitter electrode, have achieved approximately 34% increase in the critical short circuit energy. In addition, compared to the conventional assembling techniques, the new techniques make it possible to keep the lower device temperature during the normal switching operation. It has been found out that 30% reduction in die size can be expected under the conditions of having the same junction temperature increase (/spl Delta/Tj).

Advanced electro-thermal SPICE modeling of large power IGBTs

Abstract: A novel IGBT electro-thermal model is implemented for the first time in PSpice for the simulation of steady state and transient temperature dependent IGBT operation including self-heating and latchup. A thermal circuit representing the characteristics of the IGBT package is developed and validated against a finite element model and experimental results. A novel electrical IGBT model based on the Kraus model is developed to account for the electrical impact of instantaneous junction temperature variations due to self-heating. The resulting electro-thermal model is validated against experimental dc and transient FBSOA measurements.

An Experimental Assessment of Computational Fluid Dynamics Predictive Accuracy for Electronic Component Operational Temperature

Abstract: The flow modeling approaches employed in Computational Fluid Dynamics (CFD) codes dedicated to the thermal analysis of electronic equipment are generally not specific for the analysis of forced airflows over populated Printed Circuit Boards. This limitation has been previously highlighted [1], with component junction temperature prediction errors of up to 35% reported. This study evaluates the predictive capability of candidate turbulence models more suited to the analysis of electronic component heat transfer. Significant improvements in component junction temperature prediction accuracy are obtained, relative to a standard high-Reynolds number k-e model, which are attributed to better prediction of both board leading edge heat transfer and component thermal interaction. Such improvements would enable parametric analysis of product thermal performance to be undertaken with greater confidence in the thermal design process, and the generation of more accurate temperature boundary conditions for use in Physics-of-Failure based reliability prediction methods. The case is made for vendors of CFD codes dedicated to the thermal analysis of electronics to consider the adoption of eddy viscosity turbulence models more suited to board-level analysis.Copyright © 2003 by ASME

Thermal modeling and measurement of AlGaN/GaN FETs built on sapphire and SiC substrates

Abstract: We present thermal modeling and measurement results of AIGaN/GaN Heterojunction Field Effect Transistors (HFETs) fabricated on sapphire and SIC substrates. The temperature profiles on the device surface were calculated using in-house codes PAMICE and UNITHERM. These 3-D codes allow us to compute temperature at any location on and inside the device. Thermal measurement was performed using nematic liquid nystal thermography. This technique is nondestructive and can be applied while the device is in operation condition. It has suhmicron spatial resolution and +l0C temperature accuracy. In addition to temperature measurement, the technique can also be employed to detect hot spots that are possibly caused by defects. For the devices studied, current versus voltage was first measured. The results indicate that these devices behave nicely. Measured peak temperatures agree well with the calculated ones. Since sapphire has much lower thermal conductivity than Sic, AlGaN/GaN/sapphie device has higher thermal resistance than AlGaN/GaN/SiC device. A linear relationship between temperature and power was observed for both types of devices. AIGaNiGaN devices are known to have superior high power capability at high frequency. Thus, thermal modeling and measurement are valuable in determining the junction temperature and subsequently to modify device and package design so as to keep the junction temperature within acceptable range. lotroduction

Power semiconductor device

Abstract: PROBLEM TO BE SOLVED: To overcome such a problem that the power cycle life of a power semiconductor is short because of much variation of junction temperature that follows operation stop, load fluctuation, etc SOLUTION: A power semiconductor device comprises a power module where a rear pattern is soldered to a heat sink while a power switching semiconductor chip is soldered to a main circuit pattern which is formed on a front main surface with its controller provided The temperature of the power module is detected with a temperature detecting element (10) If the detected temperature is equal to the prescribed point or below, the power module is heated by a heating means As the heating means, a gate resistance (13), for example, is raised

Software determination of LED brightness and exposure

Abstract: The junction temperature of an LED is determined. This result is used to determine an initial brightness value of the LED. The initial brightness value is derated by a long-term degradation amount that is determined using a stored indication of the lifetime total on time. The derated brightness value is used to determine an exposure for a capture system. The junction temperature is determined by measuring the ambient temperature and then keeping a running junction temperature determined from the on and off times.