Showing papers on "MOSFET published in 1976"

A computer-aided design model for high-voltage double diffused MOS (DMOS) transistors

Abstract: High-voltage double diffused metal-oxide semiconductor transistors (DMOST's) have been fabricated with drain-source breakdown voltage greater than 200 V. This paper describes an experimental and theoretical study of the current-voltage behavior of these devices leading to a two-component MOS field effect transistor (MOSFET)-resistor model appropriate for computer-aided circuit design. The effects of velocity saturation, mobility reduction, and nonuniform impurity concentration in the channel, and of spreading resistance in the drift region are considered. Parameter extraction for experimentally characterizing these effects is described. Comparison of experimental and theoretical results shows that the model accurately predicts the device I/V characteristics. The range of validity of the model is limited primarily by high current saturation effects.

Protective circuit and device for metal-oxide-semiconductor field effect transistor and method for fabricating the device

Abstract: A protective circuit comprises a metal-oxide-semiconductor field effect transistor (MOSFET) to be protected, and a depletion-type MOSFET the gate and source of which are connected to each other and the souce of which is connected to the gate of the MOSFET to be protected, whereby the protective circuit which is suitable for a high-speed operation is completed.

VMOS Floating gate memory device

Abstract: A semiconductor programmable read only memory device (PROM) utilizes an array of memory cells each having an area basically defined by the intersection of a bit line and a word address line. On a substrate of one conductivity type is an upper layer of material of the opposite conductivity within which are diffused bit lines of the same conductivity material as the substrate. The crossing address lines are conductive material formed on an insulating layer that covers the diffused bit lines and the upper layer. Each cell is a single transistor element in the form of a V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of threshold logic. Each MOSFET is formed by a V-shaped recess at the intersection of each bit line and address line that extends through the diffused bit line, (which serves as the transistor drain) and into the substrate (which serves as the source and ground plane of the device). A similarly V-shaped floating gate is isolated below and above the crossing bit and address lines by thin oxide layers. Data is written into the cell when hot electrons are injected into the gate oxide near the drain junction and attracted to the floating gate which has been charged positive by capacitance coupling from the word line. The hot electrons are generated from the channel current via impact ionization at the pinched-off drain junction.

Method for fabricating diffusion self-aligned short channel MOS device

Abstract: A diffusion self-aligned, short channel device may be fabricated by ion implantation of an n-type channel region within a p-type substrate. A p-type dopant is then implanted in and driven through a portion of the n-type channel region to form an impurity region. A diffusion self-aligned n-type channel region is then disposed in the p-type impurity region and in the n-type channel region. The method allows for the simultaneous fabrication of a channel implanted MOSFET as well as a standard MOSFET. The resulting diffusion self-aligned, short channel device is a high gain, high speed small device which can be simply combined and fabricated with channel-implanted depletion devices and low body effect devices in an integrated circuit.

p-MOSFET parameters at cryogenic temperatures

Abstract: p-channel MOSFET parameters measured at 300 K, 77 K, and 4.2 K are discussed; these include I-V characteristic curves, channel conductance, transconductance, threshold voltage, field effect mobility, and forward and reverse p+n junction characteristics. Some qualitative explanations of the dependence of the data on temperature and substrate doping concentration are given. Interesting LHe phenomena are highlighted and discussed in terms of accepted solid state models.

LSI layout and method for fabrication of the same

Abstract: An LSI layout includes a logic function section and a series connection array of two MOSFETs, one end of which array is coupled to a power source voltage and the other end of which array is coupled to ground potential. A fixed logic output is produced at a junction point of the two MOSFETs by providing one MOSFET as an enhance-type MOSFET and providing the other MOSFET as a depletion type MOSFET. A logic circuit is provided which is connected with the junction point of the MOSFET array and with the logic section and is operable to couple the output of the logic section to an output side thereof. Two logic sections may be respectively associated with two logic circuits one of which is operable to couple the output of one logic section to an output thereof for its practical use and the other of which is operable not to couple the output of the other logic section to an output side thereof. The selection of the used section and the unused section is determined by the selection of either one of MOSFETs to depletion type. The LSI layout further may include a circuit section including MOSFETs. In that case, a single mask may be used in introducing a selected MOSFET of the MOSFET array and selected MOSFETs of the circuit section as depletion types. Such an LSI layout is suitable for the manufacture of many different kinds of LSI layouts with a minimized number of fabrication masks.

Manufacture of field effect semiconductor device

Abstract: PURPOSE:To obtain a high dielectric strength as well as a high output by forming a depletion layer to enhance the drain dielectric strength inside the substrate and connecting in series the input MOSFET and the output junction type FET

Mos-input buffer with hysteresis

Abstract: An MOS input buffer circuit includes an input connected to the gate electrode of an enhancement mode input MOSFET. The drain of the input MOSFET is connected to the output of the input buffer circuit. The source of the input MOSFET is connected to the drain of a second depletion mode MOSFET having its source connected to ground and its gate connected to a V DD voltage conductor. A load circuit is coupled between the V DD voltage conductor and the output, and consists of an enhancement mode MOSFET and a depletion load MOSFET coupled in series between output and V DD voltage conductor. A third depletion mode MOSFET has its drain connected to the V DD voltage conductor, its source connected to the source of the input MOSFET, and its gate connected to the output. The positive gain (or negative slope) portion of the switching characteristic of the input buffer circuit extends substantially all the way between the high and low output levels.

Characteristics of the Gallium-doped infrared sensing MOSFET (IRFET)

Abstract: The operation and characteristics of the indium-doped infrared sensing MOSFET(IRFET) in the 2.0- to 7.0-µm wavelength range are described. Responsivities of 4.8 mA/µJ are easily achieved using relatively large devices with small W/L ratios. Determination of the thermal emission rate of the indium center in silicon indicates that operating temperatures of lower than 50 K are required. Application considerations in large-scale integrated infrared imaging arrays are discussed. The measurement of the thermal emission rate and photoionization cross section of indium also demonstrates the capability of the MOSFET device structure in characterizing shallower level impurity centers in silicon.

Freeze-out effects on n-channel MOSFET's

Abstract: Surface admittance measurements have been C:L.P- ried out on (1 0 0) oriented 1-ohm-cm n-channel silicon MCIS- FET's in the freeze-out regime. The freeze-out temperature $.e- curateiy determines the amount of compensation. Measureme!l~lts at different frequencies yield different freeze-out temperatwes which in turn are used to determine the acceptor level enerycy. Thus the admittance measurements in the freeze-out reghne provide a useful tool for probing impurity levels that exist in the energy gap and identifying bulk impurities through surface measurements. A discrepancy between the measured accepttor level energy and the universally accepted one is shown to be due to a large stress that develops because of thermal mismatch he- tween the substrate and the header. LIST OF SYMBOLS Area of the device. Elastic stiffness constants. Total capacitance of the device in deep accu- mulation. Accumulation layer capacitance. Oxide capacitance. Bulk capacitance. Thickness of the silicon chip. Oxide thickness. Thickness of the kovar header. Deformation potential. Electronic charge. Young's modulus. Young's modulus for silicon. Young's modulus for the header. Acceptor level energy. Fermi level.

Linear integrated impedance with depletion MOSFETs - uses drawn-source series with each FET gate coupled to its drain or source

Abstract: The linear integrated impedance consists of a chain of depletion type MOSFets. The MOSFETs are coupled together in drain-source series. The gate of each MOSFET in the series chain is connected directly to its own source or drain. If two series-coupled MOSFETs alone are used, their two gates are connected directly to their junction point. The advantage of using depletion type MOSFETs with their gates coupled to their sources or drains, as compared to enriched-type MOSFETs, is that the impedance of the transistors depends only on the source-substrate voltage, thereby allowing a more linear impedance to be constructed over a larger range.

The buried oxide MOSFET—A new type of high-speed switching device

Abstract: A MOSFET of novel structure is proposed, which has a potential advantage on its switching speed The new structure is similar to that of SOS-MOS which essentially eliminates the junction capacitance of the MOSFET This structure is fabricated by simultaneous deposition of single and polycrystalline silicon over silicon with selective oxidations already in place The fabrication process and dc characteristics of the new devices are described The speed-power characteristics are also evaluated by computer simulations

Range switching circuit for solid state electrometer

Abstract: A range switching circuit for a solid state electrometer, e.g., for use in radiacmeter, includes a substantially symmetrical circuit having an n-channel MOSFET and an NPN transistor in one branch and a p-channel MOSFET and a PNP transistor in the other branch. The electrometer includes an operational amplifier with two high value resistors in the feedback path. A latching reed relay selectively shorts out one of the feedback resistors when one of the transistors is gated on by the corresponding MOSFET.

Optical studies of the back‐channel leakage in N‐channel MOSFET on silicon‐on‐sapphire (SOS)

Abstract: Internal photoemission studies of the Si‐sapphire interface of N‐channel transistors fabricated on silicon‐on‐sapphire (SOS) indicate that the leakage current observed in such devices after exposure to ionizing radiation is due to holes trapped in the sapphire close to the silicon interface. These holes can be removed by recombination with electrons photoinjected into the sapphire from the silicon. The much smaller preirradiation N‐channel leakage cannot be removed by electron photoinjection and is therefore thought to have a different origin.

Method for injecting charge in field effect devices

Abstract: A method is presented for accelerating the injection of minority carriers into an insulating layer overlying a semiconductor substrate under conditions less severe than required to produce impact ionization. The method is useful in characterizing parameters of field effect integrated circuit components subject to various charge instability mechanisms and may also be useful as a means for altering charge conditions in various non-volatile memory devices. A field effect device structure comprising a semiconductor p-n junction adjacent to an insulated gate electrode is utilized in which a depletion region is created under the gate electrode in the presence of alternating forward and reverse biasing of the p-n junction. During the forward bias condition minority carriers are injected into the semiconductor substrate adjacent to the gate electrode structure. During the reverse bias condition previously injected free minority carriers are accelerated by the depletion field produced by the gate electrode such that significant quantities of carriers exceed the semiconductor/insulator barrier potential and are injected into the insulator. The presence of traps in the insulator allows the capture of some of the minority carriers causing a charge to be built up in the insulator which reduces the effective field in the insulator which reduces the effective field in the semiconductor caused by the gate electrode potential. This effect in an MOSFET results in a reduction of threshold voltage. The charge injection technique may be used in combination with majority charge injection techniques, such as drain avalanching, to provide a re-writable non-volatile memory element.

54)mos type semiconductor integrated circuit

Abstract: PURPOSE:To achieve the improvement in the noise performance of a short channel MOSFET by using one of HfO2 Al2O3, Nb2O5, Ta2O5 to a gate insulation film.

Method for making reliable MOSFET device

Abstract: A substantial increase in the reliability of metal-oxide-semiconductor field effect transistor (MOSFET) devices having a thin gate dielectric is achieved by providing a thin film of phosphosilicate glass (PSG) on the thin dielectric and completely covering the PSG layer with the gate metallization. The metallization extends over a thick film of phosphosilicate glass which is disposed on the thick insulator covering the source and drain regions.

Integrated circuit with resistance element

Abstract: PURPOSE:Applying multicrystal silicon layer including oxygen as surface protection film of MOSFET, connecting a part of the multicrystal silicon layer with conductor layer having chmic contact and gate electrode, the layer thus formed is used as protection resistance.

Complementary MOS logic circuit has inverter with two MOSFETs - in drain-drain series and depleted types gate connected to its source

Abstract: The complementary MOS logic circuit has an inverter which is constructed from two complementary MOSFETs which are connected together at their drains to a common output terminal (3) and are connected by their sources to the oppositely-poled supply terminals (4, 6). The input signal (5) is applied to the MOSFET at the first gate. The second MOSFET (2) is depleted and has its gate connected to its source. The advantage of the logic lies in its avoiding delays arising from capacitance when connected into a chain of logic elements. The logic also has increased packing density.

Reliable MOSFET device and method for making same

Abstract: A substantial increase in the reliability of metal-oxide-semiconductor field effect transistor (MOSFET) devices having a thin gate dielectric is achieved by providing a thin film of phosphosilicate glass (PSG) on the thin dielectric and completely covering the PSG layer with the gate metallization. The metallization extends over a thick film of phosphosilicate glass which is disposed on the thick insulator covering the source and drain regions.

A Low Drift MOSFET Operational Amplifier A R Z

Abstract: A R Z is an operational amplifier with very low drift, built in standard MOSFET technology. Input offset voltages less than 3 ¿volts and drift values of this offset voltage less than 0.05 ¿volt/°C are measured.

Integrated oscillator with two complementary MOSFET's - one MOSFET acts as switch with resonant circuit and other MOSFET as load

Abstract: The integrated MOSFET oscillator has two MOSFETs in drain/source series: the first (2) acts as switch and is an enriched type, whilst the second (3) acts as a load and is a depletion type. The resonant circuit is connected between the gate of the MOSFET switch and the junction between the two MOSFETs. This resonant circuit may consist of a quartz crystal (7) or an inductor in parallel with the resistor (8) earthed by a capacitor (9, 10) at each end. The advantage lies in the oscillator's large frequency constant and is therefore especially suitable for closks and ultrasonic remote controls.

Field effect transistor with high withstand voltage

Abstract: PURPOSE:To provide a double dispersion-type MOSFET which has a high withstand voltage of some 500V in terms of drain withstand voltage and has an onvoltage maintained low.

Grooved Gate MOSFET

Abstract: Grooved Gate type MOS FET's which realize a short channel device with high punch-through breakdown voltage and little threshold voltage (VT) fluctuation, are fabricated by using a promising photoresist technique. A proposed, self-aligned gate MOS FET structure (Grooved Gate MOS FET) is based on two-dimensional analyses of short channel devices. A characteristic feature of the device is negative source and drain junction depth. The fabricated 21 stage ring oscillator displays a high circuit performance for delay and power product of 0.12 pJ.

The manufacturing method of flattshaped fielddeffect transistor

Abstract: PURPOSE:In flat-shaped MOSFET manufacturing used in RAM and so on, this intends to improve negative resisting pressure to prevent the contact between field doping range and source drain range.

Insulateddgate type fet

Abstract: PURPOSE:To reduce boundary charge between a semiconductor substrate and a gate film, and to lower a threshold voltage by using a thermal oxide film of multicrystal silicon as a gate film in a MOSFET.

C A D Models of MOSFET Transistors and their Parameter Acquisition on an Automatic System

Abstract: We present a parameter automatic acquisition system (S I A M) applied to C A D models of MOSFET transistors. The results are obtained on P channel and N channel, S O S and bulk devices.