Showing papers on "Multiplexer published in 1996"

Vehicle monitoring system

Abstract: The vehicle monitoring system uses a plurality of video cameras mounted on various location of a vehicle to detect and display objects not readily visible to the vehicle operator. In particular, video cameras are placed on each side of the vehicle and, preferably, on the rear portion of the vehicle. Each camera is connected to a display unit and/or a video recorder through a video multiplexer which is controlled by a main controller. The views from different cameras are displayed or recorded in response to the position of a turn signal control switch. Alternatively, the cameras can be activated when a vehicle alarm is triggered or when the vehicle is hit from the behind.

Impact of crosstalk in an arrayed-waveguide multiplexer on N/spl times/N optical interconnection

Abstract: The impact of crosstalk in an arrayed-waveguide N/spl times/N wavelength multiplexer is investigated precisely in relation to its application to wavelength-routing N/spl times/N all optical networks. In such systems multiple crosstalk light which has the same wavelength as the signal results in signal-crosstalk beat noise. We confirm that the noise is Gaussian and obtain the relation between crosstalk and power penalty. It is shown that the crosstalk must be less than -38 dB for a 16/spl times/16 system to keep the power penalty below 1 dB at a bit error rate of 10/sup -9/.

Top-down pass-transistor logic design

Abstract: The pass-transistor based cell library and synthesis tool are constructed, for the first time, to clarify the potential of top-down pass-transistor logic. The entire scheme is called LEAP (Lean Integration with Pass-Transistors). The feature of a pass-transistor based cell is its multiplexer function and the open-drain structure. This cell has the flexibility of transistor level circuit design and compatibility with conventional cell based design. An extremely simple cell library with only seven cells combined with a synthesis tool called "circuit inventor" is compared with the conventional CMOS library that has over 60 cells combined with the state-of-the-art logic synthesis. The results show that the area, delay, and power dissipation are improved by LEAP and that the value-cost ratio is improved by a factor of three. This demonstrates that LEAP has the potential to achieve a quantum leap in value of LSI's while reducing the cost. Key issues which have to be cleared before pass transistor logic is used as the generic logic scheme replacing CMOS are also discussed.

Silica-based optical integrated circuits

Abstract: Silica-based integrated optical waveguide technology is reviewed. Low loss and manufacturable waveguides are made by chemical vapour, flame hydrolysis and electron beam deposition. Fibre to fibre insertion loss is as low as 0.3 dB for a 6 cm long waveguide. Bragg reflective add-drop filters are made with gratings formed by ultraviolet irradiation. The waveguide grating router has found important application as a multiplexer in dense wavelength multiplexed communications systems. Multiplexers with wide pass bands and stop bands are made with Fourier filters: these filters consist of a chain of alternating couplers and delaying arms. The good performance of waveguide grating routers and Fourier filters is due to the high degree of path delay and coupler control achievable by and processing in this technology.

Flat spectral response arrayed-waveguide grating multiplexer with parabolic waveguide horns

Abstract: An eight-channel flat spectral response arrayed-waveguide grating multiplexer with parabolic waveguide horns has been fabricated on a planar lightwave circuit (PLC). A double-peaked intensity distribution is formed at the slab interface by the parabolic waveguide horn. A 1 dB bandwidth of 98 GHz, 3 dB bandwidth of 124 GHz and 20 dB bandwidth of 196 GHz are obtained for 200 GHz channel spacing. The crosstalk to neighbouring channels is less than –27 dB and the on-chip insertion losses range from 6.1 to 6.4 dB, respectively.

Solid-state image sensor with focal-plane digital photon-counting pixel array

Abstract: A solid-state focal-plane imaging system comprises an N×N array of high gain, low-noise unit cells, each unit cell being connected to a different one of photovoltaic detector diodes, one for each unit cell, interspersed in the array for ultralow level image detection and a plurality of digital counters coupled to the outputs of the unit cell by a multiplexer (either a separate counter for each unit cell or a row of N of counters time shared with N rows of digital counters). Each unit cell includes two self-biasing cascode amplifiers in cascade for a high charge-to-voltage conversion gain (>1 mV/e - ) and an electronic switch to reset input capacitance to a reference potential in order to be able to discriminate detection of an incident photon by the photoelectron (e - ) generated in the detector diode at the input of the first cascode amplifier in order to count incident photons individually in a digital counter connected to the output of the second cascode amplifier. Reseting the input capacitance and initiating self-biasing of the amplifiers occurs every clock cycle of an integratng period to enable ultralow light level image detection by the array of photovoltaic detector diodes under such ultralow light level conditions that the photon flux will statistically provide only a single photon at a time incident on any one detector diode during any clock cycle.

16-channel optical add/drop multiplexer consisting of arrayed-waveguide gratings and double-gate switches

Abstract: An optical add/drop multiplexer that enables full access to 16 individual wavelength channels has been fabricated on the planar lightwave circuit (PLC). The device consists of four arrayed-waveguide gratings which are connected through 16 double-gate thermo-optic switches. The crosstalk characteristics of the optical switches have been improved by adopting a double-gate configuration. The on-off crosstalks from main input or add port to main output or drop port are less than -28.4 dB and the on-chip insertion losses are 7.8-10.3 dB, respectively.

An 8.8-ns 54/spl times/54-bit multiplier with high speed redundant binary architecture

Abstract: A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is developed. This architecture enables one to convert a pair of partial products in normal binary (NB) form to one RE number with no additional circuit. We improved the RB adder (RBA) circuit so that it can make a fast addition of the RB partial products. We also simplified the converter circuit that converts the final RE number into the corresponding NE number. The carry propagation path of the converter circuit is carried out with only multiplexer circuits. A 54/spl times/54-bit multiplier is designed with this architecture. It is fabricated by 0.5 /spl mu/m CMOS with triple level metal technology. The active area size is 3.0/spl times/3.08 mm/sup 2/ and the number of transistors is 78,800. This is the smallest number for all 54/spl times/54-bit multipliers ever reported. Under the condition of 3.3 V supply voltage, the chip achieves 8.8 ns multiplication time. The power dissipation of 540 mW is estimated for the operating frequency of 100 MHz. These are, so far, the fastest speed and the lowest power for 54/spl times/54-bit multipliers with 0.5-/spl mu/m CMOS.

WDM multiplexer-demultiplexer using Fabry-Perot filter array

Abstract: A compact WDM optical device can demultiplex an optical laser signal containing several different wavelengths corresponding to particular channels, and, in reverse operation operate as a multiplexer to interleave several different wavelengths into a multiplexed multi-channel optical laser signal with improved insertion loss characteristics. The optical device includes a linear array of passive resonant optical cavities, in the form of Fabry-Perot filters, extending in a lateral direction and an integral array of associated microlenses extending in the lateral direction. Each microlens has a center which is offset from the central longitudinal axis of an associated Fabry-Perot filter to reflect laser radiation through the device. Each optical cavity is tuned by adjusting the longitudinal dimension thereof to a particular wavelength contained in the multi-channel optical signal. A stepped-wavelength steered laser radiation source for the optical device uses a VCSEL array with offset microlenses. With an additional row of microlenses the optical device can be used for wavelength routing and channel dropping applications. A stepped-wavelength WDM VCSEL array can be similarly organized to form a WDM combiner or multiplexer.

Unified program guide interface

Abstract: Analog and digital video signals are each representative of a picture and each may carry program guide information. A demultiplexer has the digital video signal as an input and the program guide information as an output. A demodulator has at least a luminance component of the analog video signal as an input and the program guide information as an output. A microprocessor, a video graphics adapter, the demultiplexer and the demodulator are interconnected by a data bus. Either of the program guide outputs is transferable to the video graphics adapter, which formats a graphics video signal representative of the program guide information. The graphics video signal and a selected one of the video signals are inputs to a multiplexer, which outputs a combined video signal representative of both the program guide information and the picture represented by the selected video signal.

Compact all-fiber add-drop-multiplexer using fiber Bragg gratings

Abstract: A novel compact all-single-mode fiber add-drop-multiplexer for dense wavelength-division-multiplexing systems is demonstrated. The device consists of a polished fiber coupler with identical Bragg gratings within the interactive length. The multiplexer operation has been theoretically analyzed and calculated transmission and reflection spectra are given. A fabricated prototype device shows good performance, but suffers from a high-insertion loss of 7 dB, which is due to the long but imperfect coupling region and can be drastically reduced in principle. A return loss >30 dB, coupling efficiency=99%, and bandwidth at FWHM /spl Delta//spl lambda/=1.2 mn was measured.

Crosstalk in multiwavelength optical cross-connect networks

Abstract: Optical crosstalk in multiwavelength optical cross-connect (multi-/spl lambda/ OXC) networks is studied. Two crosstalk mechanisms, interband and intraband crosstalk, caused by nonideal wavelength demultiplexing and space switching, are identified in this work. Their nature and accumulation behaviors are studied in detail. It has been established that the intraband crosstalk, where the crosstalk elements fall within the signal wavelength carrier band, is much more deleterious to the network end-end transparency performance. Three multi-/spl lambda/ OXC node architectures realising similar optical cross-connecting functions have been analyzed. Improvements in the most damaging intraband crosstalk can be realized by introducing a wavelength selective filter between the switch outputs and the wavelength multiplexer inputs. System penalty analyses associated with the crosstalk are also carried out using realistic system and device parameters, Both simulation and statistical analysis based approaches are presented.

Tail probabilities for a multiplexer with self-similar traffic

Abstract: We consider the large buffer asymptotics of a multiplexer under two different self-similar traffic input models, viz., the infinite server model of Cox and the fractional Gaussian noise input model. In the former case the tail probabilities for the buffer content (in steady state) are shown to decay at most hyperbolically, while in the latter they are asymptotically Weibullian. Therefore, for given input rate and Hurst parameter, these dissimilar asymptotics result in vastly differing buffer engineering practices, thereby pointing to the inadequacy of the Hurst parameter as the sole parameter to characterize long-range dependence in traffic input models.

Video coding/decoding apparatus which transmits different accuracy prediction levels

Abstract: A video coding/decoding apparatus comprises a prediction circuit that divides an input video signal into large regions and small regions in a hierarchical fashion and produces a prediction signal by performing prediction region by region, a subtracter for generating a prediction error signal for a prediction signal at the lowest level, a DCT circuit for coding a prediction error signal, a quantization circuit and a variable-length encoder, a variable-length encoder for coding the prediction mode and motion vector information obtained at each level from the prediction circuit, and a multiplexer for multiplexing the code strings obtained from the variable-length encoder and dividing them into the upper-layer and lower-layer code strings to output the code strings obtained at the variable-length encoder particularly as upper-layer code strings.

Apparatus for converting moving picture stream of MPEG1 to transport stream of MPEG2

Abstract: A demultiplexer receives an MPEG1 system stream obtained by multiplexing encoded data of video and audio and separates the stream into elementary streams (ES) of video and audio. A packetizer forms packetized elementary streams (PES) of MPEG2. Finally, a multiplexer divides the stream into transport packets each having a prefixed length of 188 bytes and, after that, converts the stream to an MPEG2 transport stream (TS).

Cascaded two-stage computational SIMD engine having multi-port memory and multiple arithmetic units

Abstract: A two-stage cascaded processor engine for Digital Signal Processing (DSP) utilizing parallel multi-port memories and a plurality of arithmetic units, including adders and multiplier-accumulators (MACs) is described. The engine supports a Single Instruction Multiple Data (SIMD) architecture. Conventional cascaded processors implementing an add-multiply-accumulate-add process for Short Length Transforms have significant limitations which are removed by the invention. The two stage processor uses two multiport memories. Arithmetic units (AU) in the top stage get their operands from a top multiport RAM and arithmetic units in the bottom stage get their operands from a bottom multiport RAM. AU outputs are stored back into the same stage as multiport RAM and passed either to the next stage or the output bus. The AU outputs can be both stored back into the same stages multiport RAM or passed either to the next stage or output multiplexer, or both of the previous. The system includes and input and output bus thus allowing simultaneous input and output operations. The AUs can also get upper ends from an auxiliary input buses to allow for operations on special data such as constant coefficients with elementary subroutines. The multiple two stage processors operate in an SIMD configuration, each processor receiving the same microcoded instruction from a microstore via a microinstruction bus. Various embodiments are described.

Wavelength division multiplexing system

Abstract: An analog lightwave communication system comprises at least two optical transmitters for providing optical information signals at different optical wavelengths. A dense wavelength division multiplexer includes at least two inputs for receiving the optical information signals from the optical transmitters and multiplexes the optical information signals to a composite optical signal at an output. Each input of the dense wavelength division multiplexer comprises at least one optical resonant cavity comprising first and second reflecting materials spaced to permit resonance at a selected wavelength. A fiber optic transmission system coupled to the output of the dense wavelength division multiplexer receives the composite optical signal.

Compact multiple-valued multiplexers using negative differential resistance devices

Abstract: Quantum electronic devices with negative differential resistance (NDR) characteristics have been used to design compact multiplexers. These multiplexers may be used either as analog multiplexers where the signal on a single select line selects one out of four analog inputs, or as four-valued logic multiplexers where the select line and the input lines represent one of four quantized signal values and the output line corresponds to the selected input. Any four-valued logic function can be implemented using only four-valued multiplexers (also known as T-gates), and this T-gate uses just 13 devices (transistors) as compared to 44 devices in CMOS. The design of the T-gate was done using a combination of resonant tunneling diodes (RTD's) and heterojunction bipolar transistors (HBT's) with the folded I-V characteristic (NDR characteristic) of the RTD's providing the compact logic implementation and the HBT's providing the gain and isolation. The application of the same design principles to the design of T-gates using other NDR devices such as resonant tunneling hot electron transistors (RHET's) and resonant tunneling bipolar transistors (RTBT's) is also demonstrated.

Fiber Bragg grating array sensor system using a bandpass wavelength division multiplexer and interferometric detection

Abstract: A multiplexing approach for high-resolution sensing with Bragg gatings is described. The scheme uses a band-pass wavelength division multiplexer to separate the returned wavelengths from an array of gratings, and interferometric processing to attain high-strain resolution. A strain resolution of 1.5 nanostrain//spl radic/Hz is demonstrated, with a sensor bandwidth of 10 Hz-2 kHz for four sensors.

Arrayed-waveguide grating multiplexer with loop-back optical paths and its applications

Abstract: We present a basic configuration of an unique integrated-optic arrayed-waveguide grating (AWG) multiplexer with loop-back optical paths and demonstrate an add-drop multiplexer (ADM), a network access terminal, and a wavelength channel selector for dense-WDM ring or bus networks, as three useful examples of its attractive applications. A key device in these components is a silica-glass based 1.55 /spl mu/m polarization-insensitive 32/spl times/32 AWG multiplexer chip with 0.8 nm channel spacing which is fabricated using planar lightwave circuit (PLC) technologies. Fine operation in their new functional components is achieved by using the AWG multiplexer module having low insertion loss of 3.9 dB and low interchannel crosstalk of less than -28 dB.

Programmable array I/O - routing resource

Abstract: A programmable array having programmable logic cells, a programmable interconnect network and a programmable I/O system. Two I/O interfaces are provided for respective logic cells about the perimeter of the array. The I/O interfaces comprise input, output and enable paths. Each of these paths has an associated multiplexer. An I/O routing network is positioned about the perimeter of the array. Conductors connecting the I/O interface multiplexers to the programmable interconnect network also intersect, and can be programmably connected to, buses of the I/O routing network.

Gate array with fully wired multiplexer circuits

Abstract: A gate array architecture adapted for serial multiplexer-based circuits In one embodiment, the gate array contains base cells having functional but isolated serial multiplexer circuits therein In another embodiment, a base cell contains a single serial multiplexer circuit divisible into varying-sized (size corresponding to the number of inputs) derivative serial multiplexer circuits In either embodiment, the serial multiplexer circuits within the base cell may be formed from P- and N-channel transistors of varying size The transistor sizes are chosen to optimize the efficiency of serial multiplexer-based circuits

Multiplexer and demultiplexer

Abstract: A multiplexer includes an n-th stage as a final output stage (n=integer, 2≦n); j stages (j=integer, 1≦j≦n-1), the n-th stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the clock signal with the serial data; and a j-th stage including m n-j-1 (m=integer, 2≦m) multiplexer blocks, each multiplexer block including D flip-flops and having data input terminals for receiving m parallel data inputs and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, and converting the parallel data into serial data in response to the second clock signal. The multiplexer further includes a variable delay circuit connected to the data input terminal of each multiplexer block in one of the second to the n-th stages for delaying the data input by a variable delay time. Therefore, even when the delay times of the constituents of the circuit vary due to device parameters or temperature, the timing of the data input can be adjusted by the variable delay circuit.

Fabrication of 128-channel arrayed-waveguide grating multiplexer with 25 GHz channel spacing

Abstract: A 128-channel arrayed-waveguide grating multiplexer with 0.2 nm (25 GHz) channel spacing at 1.55 /spl mu/m has been fabricated using a planar lightwave circuit (PLC). The authors obtained a crosstalk of less than -16 dB to neighbouring and all other channels. The on-chip insertion loss ranged from 3.5 to 5.9 dB for central and peripheral output ports, respectively.

Phase locked loop fractional pulse swallowing frequency synthesizer

Abstract: A phase-locked loop (PLL) frequency synthesizer is described which incorporates a fractional pulse swallowing circuit. The fractional pulse swallowing circuit does not add or delete pulses but extends or shortens pulses by a fractional amount. This avoids large phase errors generated by a phase detector in the PLL. In the preferred embodiment, the PLL uses a voltage controlled oscillator (VCO) formed of a ring oscillator. The outputs of the stages of the ring oscillator are applied to input terminals of a multiplexer. The multiplexer is controlled at certain times to output a different tapped signal from the ring oscillator to effectively adjust the phase of the signal output from the multiplexer. By so controlling the multiplexer, fractional pulses are subtracted or added at intervals to either increase or decrease the average frequency of the signal output from the multiplexer. The output of the VCO is fed back to the input of a phase detector along with a reference frequency. Alternatively, the output of the pulse swallower, and not the VCO, provides the feedback signal for the phase detector.

Add/drop multiplexer

Abstract: A number of add/drop multiplexers comprising passive optical components for wavelength division multiplexing are described. These add/drop multiplexers are particularly adapted for use in branching units (10) of such networks to allow signals passing along fibres (1, 2, 11, 12) of a main trunck between terminal stations (20, 30) to be dropped to and added from a spur station (40), the design of the add/drop multiplexers allowing a reduced number of spur fibres (3, 13) to be used as signals are routed between trunk fibres (1, 2, 11, 12) at spur fibres (3, 13) according to carrier wavelength.

System and method for on-chip debug support and performance monitoring in a microprocessor

Abstract: User-configurable diagnostic hardware contained on-chip with a microprocessor for the purpose of debugging and monitoring the performance of the microprocessor. Method for using the same. A programmable state machine is coupled to on-chip and off-chip input sources. The state machine may be programmed to look for signal patterns presented by the input sources, and to respond to the occurrence of a defined pattern (or sequence of defined patterns) by driving certain control information onto a state machine output bus. On-chip devices coupled to the output bus take user-definable actions as dictated by the bus. The input sources include user-configurable comparators located within the functional blocks of the microprocessor. The comparators are coupled to storage elements within the microprocessor, and are configured to monitor nodes to determine whether the state of the nodes matches the data contained in the storage elements. By changing data in the storage elements, the programmer may change the information against which the state of the nodes is compared and also the method by which the comparison is made. The output devices include counters. Counter outputs may be used as state machine inputs, so one event may be defined as a function of a different event having occurred a certain number of times. The output devices also include circuitry for generating internal and external triggers. User-configurable multiplexer circuitry may be used to route user-selectable signals from within the microprocessor to the chip's output pads, and to select various internal signals to be used as state machine inputs.

Design considerations of superconductive input multiplexers for satellite applications

Abstract: This paper describes the evolution and development of low power superconductive filters and multiplexers for satellite applications under the HTSSE-II program. Experimental results and tradeoffs are presented for thin film and dielectric loaded HTS multiplexer configurations, leading to the development and implementation of a fully integrated four-channel C-band HTS input multiplexer. Measured data shows performance comparable to conventional technology and promise of large reduction in mass and volume of such equipment. The multiplexer is scheduled to fly as part of the HTSSE-II package on the ARGOS satellite in 1996.

Closed loop congestion control using a queue measurement system

Abstract: A queue length measurement device that is comprised of a number of queues that are capable of holding data cells. A differential counter is coupled to each queue. The counter is incremented when a cell is written into the queue and decremented when a cell is read from the queue. An interval measurement device, coupled to the differential counter, generates a pulse to reset the counter at fixed intervals equivalent to n cells time (where n is the maximum number of cells the queue counter can measure). A multiplexer is coupled to the multiple differential counters. A transfer control circuit coupled to the interval measurement device selects the appropriate queue measurement to be output from the multiplexer to the other switch elements. A system and methodology provide for queue flow statistics and closed loop control of cell flow into the queue. A congestion control system is provided comprising a queue (having an input and an output, and capable of storing and outputting a plurality of data cells), an input processor (for coupling a plurality of data cells to the queue input), an output processor, an interval measurement device (generating a pulse at predetermined intervals), and differential queue length generation logic. The output processor, couples to the queue output, for receiving a plurality of data cells from the queue, which generates a queue change in size signal in response to determining for each of the predefined intervals of the difference between a present and a previous queue length.

Video/audio data supplying device

Abstract: When the input output controller 22 receives request data through the modem 42, the input output controller 22 controls the memory controller 25 to retrieve an AV stream and a BGV stream from the memories and to transfer the streams to the multiplexer 30. The memory controller 25 retrieves a BGV stream from the BGV memories 26a, 26b, and 26c and an AV stream from the AV memories 27a, 27b, and 27c. When receiving the BGV stream and the AV stream, the multiplexer 30 divides the AV stream into a lyric stream and a music stream. The multiplexer 30 composes the lyric stream and the BGV stream into a video stream. The multiplexer 30 time-divisionally multiplexes the video stream and the music stream and outputs the multiplexed stream as a video/music stream.