Showing papers on "p–n junction published in 1979"

A majority‐carrier camel diode

Abstract: A majority‐carrier diode concept is described in which current flow is controlled by a potential hump in the bulk of a semiconductor. Devices of this type, called camel diodes, having ideality factors <2 have been realized using low‐energy ion implantation.

The importance of surface recombination and energy-bandgap arrowing in p-n-junction silicon solar cells

Abstract: Experimental data demonstrating the sensitivity of open-circuit voltage to front-surface conditions are presented for a variety of p-n-junction silicon solar cells. Analytical models accounting for the data are defined and supported by additional experiments. The models and the data imply that a) surface recombination significantly limits the open-circuit voltage (and the short-circuit current) of typical silicon cells, and b) energy-bandgap narrowing is important in the manifestation of these limitations. The models suggest modifications in both the structural design and the fabrication processing of the cells that would result in substantial improvements in cell performance. The benefits of one such modification-the addition of a thin thermal silicon-dioxide layer on the front surface-are indicated experimentally.

Quantum efficiency of the p-n junction in silicon as an absolute radiometric standard.

Abstract: The most widely used detector of optical radiation is the silicon photodiode. The physics of this device is well under­ stood, and its technology is quite advanced. It is based on the p-n junction in silicon, which has been the subject of intense and thorough study because of its widespread application in solid state electronics and solar cells. When a silicon photodiode is used to measure optical ra­ diation in absolute units, its calibration is not based on the physics of silicon. Instead the calibration is based on the thermal physics of either blackbody radiators or electrical substitution radiometers. The highest accuracy currently demonstrated for either of these techniques is on the order of one-tenth of 1%, and it was achieved only with considerable difficulty. The accuracies achieved in more routine calibra­ tions do not approach this level. For this reason, and be­ cause silicon technology is so highly advanced, it has been suggested that calibrations of comparable or even higher ac­ curacy could be obtained directly from the electrical and/or optical characteristics of the photodiode itself. In fact, in the red portion of the visible spectrum the sum of the specular reflectance and the external quantum efficiency of shallow junction silicon photovoltaics falls within a few tenths of 1% of unity. Therefore, all that is needed is a physical model that describes the small defect in the internal quantum efficiency of this type of device, and which is in a form suitable for high accuracy applications. The remainder of this Letter will be devoted to this task. It is convenient to divide the typical silicon photovoltaic detector into four regions: the antireflection coating; the front diffusion region; the bulk region; and the rear diffusion region. The following analysis is restricted to wavelengths for which negligible radiation is absorbed in the antireflection coating. This condition is satisfied throughout the visible and near ir by grown SiO2 coatings, but not by vacuum deposited coatings of the same material. Within the front diffusion region, the doping concentration and minority carrier diffusion length vary by many orders of magnitude. The exact nature of these variations is not readily determined, so neither analytic nor numerical solutions of the minority carrier diffusion equation can be used. However, the contribution of this region to the internal quantum effi­ ciency at wavelength λ can be expressed as

Production of semiconductor device

Abstract: PURPOSE:To obtain a semiconductor device where a varactor diode and a PIN diode are stable and the junction having a density distribution is steps can be formed. CONSTITUTION:A P layer is formed on a N-type epitaxial wafer by epitaxial growth, and next, a P layer is formed from the P layer surface by thermal diffusion, or a N layer is formed on the P-type epitaxial wafer by epitaxial growth. Next, N layer is formed from the N layer surface by heat diffusion, thereby forming PN junction.

Diffusion of dopant from optical coating and single step formation of PN junction in silicon solar cell and coating thereon

Abstract: The PN juncture in a silicon chip and an oxide coating on its surface are simultaneously formed from clear solution derived from titanium alkoxides, water, alcohol, a suitable acid, and a P or N dopant compound by partial hydrolysis and polymerization. The solution is applied to the surface of a silicon chip. The chip is then heated which converts the solution to a solid oxide coating which meets the antireflective optical film requirements and induces the migration of the dopants into the chip, forming a PN junction in the chip. The method also provides deep and uniform junction formation or diffusion without resulting in excessive carrier concentration.

Manufacture of semiconductor device

Abstract: PURPOSE:To avoid occurrence of the distortion on the PN junction surface by giving the pressure division with the division groove provided so that it may not reach the PN junction from the surface of one side when the PN junction is formed on the semiconductor substrate and then the substrate is divided with the division groove provided. CONSTITUTION:P-type layer 12 is epitaxial-grown on N-type GaP substrate 11, and then division groove 15 is provided via dicing so that it may not reach PN junction 13 caused from the back side of large-thickness substrate 11. Then the pressure is applied from the side of layer 12 on the other surface to form split 16 toward the area where no groove 15 is formed, thus obtaining a number of light emitting elements 17 of a fixed size. In such way, no distortion is caused on PN junction surface 13 with no deterioration of the light emitting output. This method can also be applied effectively to the division of other semiconductor elements in addition to the light emitting element.

Silicon p-n junction photodiodes sensitive to ultraviolet radiation

Abstract: Experimental studies on a silicon photodiode have been carried out to achieve the performance characteristics required for applications such as spectroscopic measurements Sheet resistance was applied as a control parameter for diffusion to obtain a shallow junction less than 1 µm in depth For high ultraviolet responsivity, the diffusion layer, in which a built-in field is induced by the impurity gradient, was optimized for values of the sheet resistance of about 800-2000 Ω/□ The device responded in the wavelength range of 200-1000 nm,and had a responsivity of 0065 A/W at 200 nm In order to reduce influence of stray light in spectroscopic measurements, two types of photodiodes were fabricated with photoresponse reduced in the long-wavelength portion A p+-n-p+device was found preferable to a p+-n-n+device And the device structure with an extended electrode was desirable for high, reliable performance

Method of low dose phoshorus implantation for oxide passivated diodes in {21 100{22 {0 P-type silicon

Abstract: Low dosage phosphorus implantation regions in P-type silicon are subjected to a severe damage implant with halogen or silicon ions, preferably fluorine and chlorine. This permits anneal in a strongly oxidizing atmosphere for PN junction passivation, without concurrently inducing PN junction leakage. Oxide passivated PN junctions are formed having leakages as low as when the low dose phosphorus implants are annealed in other atmospheres, or are formed in silicon.

Lifetime of InGaAsP–InP and AlGaAs–GaAs DH Lasers Estimated by the Point Defect Generation Model

Abstract: Ageing characteristics of conventional double heterostructure lasers have been explained by extending the defect model proposed in connection with remote junction heterostructure lasers. Two major phenomena are responsible for laser degradation: One is that mobile defects remaining in the cladding layer before ageing move toward the pn junction and accumulate there during ageing. Another component is due to the mobile defects created in the active region by the non-radiative recombination of injected carriers. Using this model, the ultimate lifetime of InGaAsP–InP lasers was, for the first time, concluded to be far longer than that of AlGaAs–GaAs lasers.

Dual junction photoelectric semiconductor device

Abstract: A photoelectric semiconductor device is disclosed which exhibits a reduced spectral sensitivity in a desired wavelength zone. An N(P) type impurity region is formed in a P(N) type semiconductor substrate to establish a first PN junction functioning as a first photodiode. A P(N) type impurity region is shallowly formed in the N(P) type impurity region to establish a second PN junction functioning as a second photodiode. When the first PN junction is shunted, the photoelectric semiconductor device shows a spectral sensitivity which is reduced in the longer wavelength zone. Contrarily, when the second PN junction is shunted, the photoelectric semiconductor device shows the spectral sensitivity which is reduced in the shorter wavelength zone.

p‐n junction diodes in InP and In1−xGaxAsyP1−y fabricated by beryllium‐ion implantation

Abstract: Mesa and planar InP p‐n junction diodes have been fabricated by beryllium‐ion implantation. These devices exhibit abrupt reverse‐bias breakdowns and low leakage currents. Similar mesa diodes have been produced in In1−xGaxAsyP1−y (Eg≈1.0 eV). Diodes operated in the punch‐through mode exhibited uniform breakdown over the area of the device, without any apparent edge effects.

Passivation of p-n junction in crystalline silicon by amorphous silicon

Abstract: Hydrogenated amorphous silicon, a-Si:H, is shown to be an excellent passivant for crystalline silicon (c-Si) p-n junctions. A two-orders-of-magnitude reduction in reverse leakage current from that of a typical thermal oxide passivated junction is obtained. This is achieved through a lowering of the interface state density by hydrogenation of the c-Si surface. Superior bias-temperature stability of the passivated junctions also is observed. There is evidence that the hydrogen in the bulk of the a-Si:H can act as a hydrogen reservoir for rehydrogenation of the interface between c-Si and a-Si:H. Thermal stability of the a-Si:H is adequate for temperatures up to 500°C for 30 min, which is sufficient for most device-processing requirements. Above 550°C, significant dehydrogenation from both the interface and the bulk a-Si:H regions and an increase in leakage are observed. The passivation properties were assessed through studies of the current-voltage and current-temperature characteristics of the p-n junctions.

Field effect transistor with insulated gate electrode

Abstract: A field effect transistor of the V-MOST type in which the channel region comprises a more highly doped part which adjoins the source zone and a lower doped part which surrounds said region, said channel region adjoining the surface and surrounded by an insulation diffusion. The lower-doped part is depleted from the pn junction with the low-doped drain region up to the surface at a voltage which is lower than the breakdown voltage.

Mesa epitaxial diode with oxide passivated junction and plated heat sink

Abstract: An oxide passivated mesa epitaxial diode with an integral heat sink, and a process by which it may be fabricated. The passivation layer of highly pure thermally grown SiO 2 is formed over the mesa walls in the region of the pn junction without causing a reaction between the contact metals and their surroundings during the high temperature environment imposed during thermal growth. The heat sink is deposited after the SiO 2 passivation has been grown, replacing a polycrystalline silicon layer beneath the mesa formation which was used as a temporary structural support. Dopant, to form the pn junction, is introduced into the silicon wafer after the formation of the passivation layer but before the heat sink is deposited.

Semiconductor element with zone guard rings

Abstract: A semiconductor element having at least one pn junction and provided with zone guard rings for improving the suppression behavior of the pn junction, wherein the pn junction extends to the peripheral or side surface of the element and the first of a series of guard rings is coordinated with the pn junction and is bounded by the peripheral or side surface and by the lower planar surface of the element.

Semiconductor component with at least one planar PN junction and zone guard rings

Abstract: A semiconductor component including at least one planar PN junction formed between a first semiconductor region and a second semiconductor region, zone guard rings surrounding the first region and surrounded by the second region in order to improve the reverse-current behavior of the PN junction, and a third semiconductor region having the same conductivity type as the second region, but having a higher doping concentration than the latter provided in the second region preceding the respective edges of the guard rings on the side of the PN junction. Typically the third region is doped such that with the PN junction polarized in the blocking direction, at least one point in the third region remains at zero field strength. Additionally provided is a fourth semiconductor region between the guard rings and between the guard ring closest the PN junction and the PN junction, which has the same conductivity type as the second region, but a lesser doping concentration.

Gate protective device

Abstract: PURPOSE:To prevent the application of input voltage directly to the PN junction of diffusion resistance layer, by constituting a part of the input side of the input protection resistor with polycrystal semiconductor and other parts with conventional diffusion resistance layer. CONSTITUTION:Since the polycrystal semiconductor resistance layer 26 is located closer part to the input terminal than the diffusion resistance layer 22, the forward voltage due to noise such as undershooting or high voltage due to static electricity is fed to the diffusion resistance layer 22 in the form that is reduced with the resistance layer 26. Thus, unnecessary carrier injection from the PN junction of the diffusion resistance layer 22 is restricted and the noise margin is increased, the destruction of the PN junction is restricted and the strength withstanding the static electricity can be increased.

Dielectrically-isolated integrated circuit complementary transistors for high voltage use

Abstract: Integrated circuit complementary transistors for high voltage switching applications are fabricated in separate dielectrically-isolated pockets (12), (14) of high resistivity silicon, supported in a conductive medium (11) such as polycrystalline silicon, using surface adjacent conductivity type zones constituting emitter (19), (23), base (16), (20) and collector zones (17), (21). In one embodiment using high resistivity (75-300 ohm cm) silicon, referred to as π material, for the material of the pocket, one transistor is a PNπP device, and the other is an NPπN. In the PNπP the reverse-biased base-collector pn junction is the interface between the N base zone (16) and the π portion (12) of the collector zone. In the NPπN transistor the base-collector junction is the interface between the lightly doped π extension (14) of the base zone (20) and the N collector zone (21). A connection (32) is provided to the conductive substrate to enable application of a suitable potential thereto.

Integrated semiconductor circuit arrangement

Abstract: An integrated semiconductor circuit arrangement is provided which comprises a substrate of semiconductor material of one conductivity type, an epitaxial layer of the opposite conductivity type formed on one major surface of the substrate, the epitaxial layer having function elements such as transistors, diodes, resistances, and so forth, formed therein. A least some of these function elements are located in insulated regions provided for them which in the boundary area between the substrate and the epitaxial layer are bounded by a pn junction and which at right angles to this boundary area are bounded by oxide walls which extend through the epitaxial layer to the substrate. The oxide walls are surrounded by a resistor region of the said one conductivity type which extends through the epitaxial layer to the substrate.

Avalanche photo diode

Abstract: PURPOSE:To obtain a diode featuring a high quantum efficiency and low redoubled noise by composing the avalanche photo diode with two kinds of semiconductor crystal materials. CONSTITUTION:P -type Si layer 2 is epitaxial-grown on N -type Si substrate 1 and then covered with insulator 5. And the mesa etching is given deeper than PN junction 10 caused by drilling the opening to form concavity 6. Then N -type layer 7 is formed through diffusion on the mesa slope of concavity 6, and film 5 is renewed with the window drilled at the center part of layer 2 to form concavity 2a to layer 2 through etching. After this, P -type Ge layer 3 is epitaxial-grown on the entire surface while filling concavity 6 and 2a. Then the P-type impurity is diffused to the surface of layer 3 to form P -type Ge layer 4, and the surface of layer 4 is covered with film 5. Film 5 at the areas excluding layer 4 is removed along with layer 3 and 4 produced on the film, and surface electrode 8 is attached to remaining layer 4 with back surface electrode 9 attached to the back of the substrate.

Protection circuit for a semiconductor device

Abstract: A protection circuit for a semiconductor substrate comprises a semiconductor substrate of a first conductivity type, a first region of a second conductivity type formed in the semiconductor substrate, a second region of the first conductivity type formed in the first region, a means for applying a reverse bias to a PN junction formed between the semiconductor substrate and the first region and a PN junction formed to the first and second regions, and a wiring for electrically connecting the second region to the semiconductor device to be protected.

Field effect semiconductor device

Abstract: PURPOSE:To control a channel current by controlling the expansion of a depletion layer by utilizing light electromotive force generated at a PN junction through irradiation. CONSTITUTION:Onto the N- layer on the N layer, P-type gate layer 3 is provided, and its interval is narrow enough not to generates any channel longitudinally owing to the overlap of depletion layer 4 at the time of no irradiation. Between gates source lead-out N layer 5 is made and provided with electrode 7, and drain electrode 8 is led out from N substrate 1. Irradiating gate and channel parts generates a release voltage in the forward direction of the (pn) junction and depletion layers 4 contract to form channels inside layers 2 between facing gates 3, thereby making electrodes 7 and 8 conductive each other. The channel current can also be controlled by varying irradiation or the depth of the gate layer.

P-n junction type rectifying diode

Abstract: PURPOSE:To obtain the diode which has preferable reverse characteristics and low positive voltage drop by coating a P type layer in island shape on an N type layer on an N type layer and coating Pt thereon. CONSTITUTION:The islandlike P type layer 4 is formed on the N type epitaxial layer 2 on the N type layer 1, the Pt layer 8 is deposited thereon, and a Schottky junction is formed between the layer 8 and the layer 2. Ni electrodes 5, 6 are formed respectively on the layers 1 and 8. When a voltage is appleid between the electrodes 6 and 5 and a forward voltage is applied to the P-N junction 3, the forward current will flow in parallel with the P-N junction and the Schottky junction 7. According to this configuration, electrons are injected from the layer 1 to the layer 2, while holes are injected from the layer 4, in case of flowing the forward current, a conductivity modulation occurs in the layer 2, and the resistance of the layer 2 is produced. Accordingly, a forward current will flow with sufficiently low voltage as compared with the forward voltage drop of the Schottky junction itself, and yet sufficiently high withstand voltage and low reverse current will be retained in reverse direction.

Light emitting element of semiconductor

Abstract: PURPOSE:To enable large current operation and to increase the coupling efficiency of optical fibers, by enclosing the surrounding of the light emitting layer with semiconductor material having greater forbidden band width than that of the light emitting layer and giving the pn junction, in a surface light emission layer 12 is enclosed with the n-AlXGa1-XAs layer 11 and the p-AlXGa1-XAs layer 13 and the electrode 17 is mounted on the entire lower surface of the layer 13. Accordingly, the loght emitting layer 12 has a pn junction on the upper or lower surface and at the circumference, the boundary of the layers 11 and 13 is a pn junction. Further , the diffusion potential at the pn junction on the upper or lower surface of the layer 12 is decreased in comparison with that at the pn junction formed with the layers 11 and 13, the current is concentratingly flown in the layer 12, and the light emitting region can automatically be limited. Further, since the area of the electrode 17 can be made greater, the contact resistance can be decreased and the uniformity of the light emitting strength distribution can be improved.

Scanning-electron-beam annealing of ion-implanted p-n junction diodes

Abstract: Scanning-electron-beam annealing of ion-implanted silicon p+-n junctions over a range of beam power and exposure conditions is described. Electrical measurements have shown that electron-beam annealing can produce diode characteristics close to those of similar thermally annealed structures.

Production of photo detector

Abstract: PURPOSE:To eliminate the irregularity of light receiving sensitivity characteristic among elements from the same large-scale substrate by providing a high-density thin layer, which has the same conduction type as the substrate to be a light receiving layer and has the carrier density controlled sufficiently in surface and depth directions, on the low-carrier density n-type substrate and forming pn junctions on this layer and inside it in the pn-junction photo diode. CONSTITUTION:S ions of n-type impurity are injected onto a large-scale epi-substrate, where an n -epi-layer is provided on an n GaAs substrate, with 7X10 cm for 200 KeV and 3X10 cm for 70KeV. Next, the surface is convered with SiO2, and the substrate is subjected to heat treatment in N2 to form an n layer with a surface layer of approximately 0.4mum. Further, windows are provided selectively in SiO2, and Zn ions are injected with 1X10 cm . Then, the surface is convered with SiO2 again, and the substrate is subjected to heat treatment in N2 form a pn junction, thereby producing a device of an approximately 1 mm square. By this methode, the ion injection layer which has a carrier density distribution irregular in surface and depth directions can be formed at a depth of 0.1 to 1mum from the substrate surface, and a desired spectral sensitivity characteristic can be obtained.

Manufacture of silicon avalanche photodiode

Abstract: PURPOSE: To very easily manufacture a p-type side light incidence planar Si avalanche photodiode, by utilizing the fact that the impurity diffusion velocity in polycrystalline Si is much higher than that in single crystal Si CONSTITUTION: An annular polycrystalline Si growing nucleus 12 is made of a thin oxide film or the like on an n + -type single crysral Si substrate 1 Epitaxial growth is caused while a p-type impurity is doped into the entire surface, thereby producing a polycrystalline Si layer 13 on the nucleus 12 and a p-type single crystal Si layer 2 on the exposed substrate 1 An n-type impurity is selectively diffused into the layer 13 The layer 13 is all changed into the n-type by utilizing the fact that the diffusion velocity in the layer is high At the same time, the impurity in the substrate 1 is diffused into the layer 2 to produce an n-type region 9 surrounding the layer 13 and the nucleus 12 A challow p + -type region 3 is thus produced by diffusion in the surface part of the layer 2 while a pn junction is prevented from exerting an influence An electrode 7 is fitted on the region 3 while a reflection preventing film 14 is coated on the region 3 An insulating film 10 is coated on the surface except for the film 14 COPYRIGHT: (C)1980,JPO&Japio

Semiconductor laser device and its manufacture

Abstract: PURPOSE:To form the wave guide path which is crooked with an extremely small curvature radius by forming the optical guide layer facing the side wall of the etched concavity of the crystal substrate and nonparallel to the substrate surface. CONSTITUTION:The n-type GaAs211 and n-type GaAlAs210 are laminated, and the concavity vertical to the paper surface is provided on the surface to laminate n- type GaAs thin layer 213 and n-type GaAlAs210 are laminated. After polishing the surface of layer 214, Zn is diffused to form P -layer 215 and then p -layer 216 with gentle-sloped density through heat treatment and with electrode 217 and 218 attached. With the forward conduction, the diffusion potential of p Pn junction surface formed in layer 212 becomes higher than that of p Pn junction caused in layer 213, and thus the potential flows mainly to P-layer 219. And layer 219 features the optical guide structure if the refraction index is made higher than that of its peripheral. Layer 219 features the intensive index guiding structure held between layer 212 and 214, and thus the single mode is secured in the wave guide path featuring an extremely small curvature.

Photo electromotive force element

Abstract: PURPOSE:To establish the element of high performance and long life, by inserting the p type CdTe between the p type Cu2Te and the n type CdTe, forming pn junction in the CdTe layer, and taking the P type Cu2Te on the surface as the electrode CONSTITUTION:The n type CdTe 2 added with In is evaporated on the CdS sintering film 1 of low resistance on the aluminum porcelain 6 It is immersed for a short time in CuCl hot water solution to form Cu2-xTe thin layer 4 on the surface With heat treatment, Cu of the layer 4 is diffused to the layer 2, and the p type CdTe 3 is formed between the p layer 4 and the n layer 4 On the layer 4, the Ag anode 5 is provided in lattice shape and the In-Ga cathode 7 is placed on the film 1 A voltage is caused between the leads 8 and 8' when light is projected from the layer 4 There are two types of junctions of p Cu2-xTe-nCdTe and pCu2-xTe-pCdTe- nCdTe The latter is high in conversion efficiency, and photo current is caused at pCdTe-nCdTe homogeneous junction The p Cu2Te plays a role of the electrode only, thus it does not give direct effect on the deterioration of performance, and it becomes longer in life