Showing papers on "p–n junction published in 1994"

SiC devices: physics and numerical simulation

Abstract: The important material parameters for 6H silicon carbide (6H-SiC) are extracted from the literature and implemented into the 2-D device simulation programs PISCES and BREAKDOWN and into the 1-D program OSSI Simulations of 6H-SiC p-n junctions show the possibility to operate corresponding devices at temperatures up to 1000 K thanks to their low reverse current densities. Comparison of a 6H-SiC 1200 V p-n/sup -/-n/sup +/ diode with a corresponding silicon (Si) diode shows the higher switching performance of the 6H-SiC diode, while the forward power loss is somewhat higher than in Si due to the higher built-in voltage of the 6H-SiC p-n junction. This disadvantage can be avoided by a 6H-SiC Schottky diode. The on-resistances of Si, 3C-SiC, and 6H-SiC vertical power MOSFET's are compared by analytical calculations. At room temperature, such SiC MOSFET's can operate up to blocking capabilities of 5000 V with an on-resistance below 0.1 /spl Omega/cm/sup 2/, while Si MOSFET's are limited to below 500 V. This is checked by calculating the characteristics of a 6H-SiC 1200 V MOSFET with PISCES. In the voltage region below 200 V, Si is superior due to its higher mobility and lower threshold voltage. Electric fields in the order of 4/spl times/10/sup 6/ V/cm occur in the gate oxide of the mentioned 6H-SiC MOSFET as well as in a field plate oxide used to passivate its planar junction. To investigate the high frequency performance of SiC devices, a heterobipolartransistor with a 6H-SiC emitter is considered. Base and collector are assumed to be out of 3C-SiC. Frequencies up to 10 GHz with a very high output power are obtained on the basis of analytical considerations. >

Three-dimensional simulation of charge collection and multiple-bit upset in Si devices

Abstract: In this paper, three-dimensional numerical simulation is used to explore the basic charge-collection mechanisms in silicon n/sup +//p diodes. For diodes on lightly-doped substrates ( >

2000 v 6h-sic p-n junction diodes grown by chemical vapor deposition

Abstract: In this letter we report on the fabrication and initial electrical characterization of the first silicon carbide diodes to demonstrate rectification to reverse voltages in excess of 2000 V at room temperature. The mesa structured 6H‐SiC p+n junction diodes were fabricated in 6H‐SiC epilayers grown by atmospheric pressure chemical vapor deposition on commercially available 6H‐SiC wafers. The devices were characterized while immersed in FluorinertTM to prevent arcing which occurs when air breaks down under high electric fields. The simple nonoptimized diodes, whose device areas ranged from 7×10−6 to 4×10−4 cm2, exhibited a 2000 V functional device yield in excess of 50%.

Compound semicondutor light-emitting device

Abstract: A compound semiconductor light-emitting device includes a cubic SiC substrate, and an Ga x Al y In 1-x-y N (0≦x≦1, 0≦y≦1) layer formed on the (111) surface of the cubic-crystal SiC substrate. The surface of the Ga x Al y In 1-x-y N layer, which opposes the substrate, is an N surface, and the light-emitting device has a pn junction.

Separation and analysis of diffusion and generation components of pn junction leakage current in various silicon wafers

Abstract: An analytical method to separate the diffusion and generation components of pn junction leakage currents is developed The voltage dependence between reverse current and capacitance in pn junctions is measured, and an approximately linear relationship between current density (J) and depletion width (W) is derived In this relationship, the diffusion component corresponds to linearly extrapolated value of J at W=0, and the generation component corresponds to the rate at which J increases with W as voltage is applied This method allows both components of the leakage current to be obtained for Czochralski, epitaxial, and intrinsic gettering wafers Separated diffusion components strongly depend on silicon wafers mainly due to the change of minority carrier density and the diffusion of minority carriers On the other hand, the generation component increases with increases in the electric field applied to the junction for all wafers We found that this electric field effect on the generation component can be

Electrical properties of epitaxial 3C- and 6H-SiC p-n junction diodes produced side-by-side on 6H-SiC substrates

Abstract: 3C-SiC (/spl beta/-SiC) and 6H-SiC p-n junction diodes have been fabricated in regions of both 3C-SiC and 6H-SiC epitaxial layers which were grown side-by-side on low-tilt-angle 6H-SiC substrates via a chemical vapor deposition (CVD) process. Several runs of diodes exhibiting state-of-the-art electrical characteristics were produced, and performance characteristics were measured and compared as a function of doping, temperature, and polytype. The first 3C-SiC diodes which rectify to reverse voltages in excess of 300 V were characterized, representing a six-fold blocking voltage improvement over experimental 3C-SiC diodes produced by previous techniques. When placed under sufficient forward bias, the SC-SiC diodes emit significantly bright green-yellow light while the 6H SiC diodes emit in the blue-violet. The 6H-SiC p-n junction diodes represent the first reported high-quality 6H-SiC devices to be grown by CVD on very low-tilt-angle ( >

High withstand voltage semiconductor device

Abstract: PURPOSE:To provide a high withstand voltage semiconductor device in which withstand voltage is enhanced while realizing high integration. CONSTITUTION:PN junction between an embedded collector region 3 and a collector withstand voltage region 4 is reversely biased and the depletion layer thereof reaches a side isolation insulator region 9 for dielectrically isolating the side face of the semiconductor withstand voltage region 4. A polysilicon region 8 contiguous to the collector withstand voltage region 4 while sandwiching the side face isolation insulator region 9 has a potential closer to that of a base region 5 than that of the embedded collector region 3. Consequently, the depletion layer in the collector withstand voltage region 4 between the side face of the base region 5 and the side face isolation insulator region 9 is affected by the low potential from both sides of the base region 5 and the polysilicon region 8 and concentration of electric field is relaxed in the vicinity of the corner part between the side face and the bottom face in the base region 5. Consequently, avalanche breakdown is suppressed at that part resulting in the enhancement of withstand voltage.

Practical high efficiency bifacial solar cells

Abstract: In this paper, we present a practical process to obtain bifacial Si solar cells. These cells are made using p/sup +/nn/sup +/ structure on high-medium base resistivity, continuous emitters and with a process that maintains high bulk minority carrier lifetime. Efficiencies of 19.1% and 18.1% are achieved under standard conditions when the cell is illuminated by n/sup +/n high-low junction and when it is illuminated by p/sup +/n junction, respectively. We show that the n/sup +/n high-low junction provides a higher current density and a good ratio between generated current of each face is found to be of about 103%.

High energy heavy-ion-induced single event transients in epitaxial structures

Abstract: This paper describes numerical and experimental heavy-ion charge collection studies using P/sup +/N junctions on epitaxial layers. The numerical simulations provide insights into the basic mechanisms contributing to transient currents and charge collection in devices on epitaxial layers. This paper also presents charge collection data from /spl sim/2 GeV /sup 127/I ions incident upon P/sup +/N junctions on both bulk silicon and epitaxial layers and compares the experimental data with the simulation results. The experimental data show that charge deposited below the epitaxial layer can be collected. This work is unique and important because this GeV-energy-range /sup 127/I ion more nearly represents a cosmic ray compared to lower energy, heavy-ions in the hundreds of MeV energy range. This paper also discusses the simulation results with respect to the experimental data and charge collection models for epitaxial transistors. Additionally, a shunting model is proposed to model the early transient current responses. >

Semiconductor integrated circuit device

Abstract: PURPOSE:To enhance reliability by allowing direct measurement of the temperature of an LSI through the use of voltage fluctuation at PN junction of a transistor not selected in the formation of a required integrated circuit. CONSTITUTION:In a basic cell array 3 for inner circuit, transistors selected and not selected in the formation of circuits are arranged in matrix on a master wafer 1. A transistor 5 not selected in the formation of circuit, from among a group of transistors arranged in matrix in an I/O cell array region 2, are used selectively for monitoring the temperature. The temperature detecting transistor 5 is normally fed with a constant current and the junction voltage is detected. The fluctuation of temperature in the region of the transistor 5, and thereby of a gate array type LSI, can be detected based on the fluctuation of the junction voltage. When a signal is outputted to the outside of the LSI, connection is made with a cooling mechanism control circuit, a stand-by system switching circuit, an auxiliary system operating circuit, etc., of the LSI and an appropriate control is performed.

Monocrystalline diamond semiconductor device and several electronic components employing same

Abstract: A diamond semiconductor device has a pn junction formed by a p-type diamond semiconductor portion containing boron as an impurity and an n-type diamond semiconductor portion containing lithium as an impurity. The diamond semiconductor is formed by a diamond crystal growth on a single nucleation site on an insulating substrate. Electroluminescene takes place in the diamond crystal.

Semiconductor device with buried inverse T-type field region

Abstract: The present invention relates to a semiconductor and a method for fabrication thereof and particularly to a semiconductor having a field oxide having a shape such that the lower part is wider that the upper part. Therefore, according to the present invention, the ion implantation process for forming a channel stop region becomes unnecessary, because of the effect of accurate insulation between the devices and the pn junction area can be decreased, so that the junction capacitance becomes decreased. Furthermore, because LOCOS edge does not coincide with the junction edge, the leakage current due to the damage of the edge is not generated. Because a field oxide is of the buried inverse T-type, the effective width of the device is increased more than that of a mask. Because the bird's beak is not generated, the problem due to the narrow width can be settled.

A highly linear single p-n junction temperature sensor

Abstract: A temperature sensor based on the use of two forward-biased p-n junctions is known to exhibit good linearity. An alternative sensor configuration, based on the same principle, but employing only one p-n junction is presented in this paper. The forward current through the p-n junction is switched alternately between two fixed values, and the difference between the corresponding voltages is shown to vary linearly with temperature. This scheme eliminates the problems associated with close matching required for the two p-n junction sensors. Experimental results obtained with the proposed scheme are presented. A configuration to exploit the temperature dependence of the p-n junction incremental resistance is also presented. >

P-N junction etch-stop technique for electrochemical etching of semiconductors

Abstract: A method of electrochemical machining of micromechanical structures from a silicon substrate having both p and n-type regions in hydrofluoric electrolyte solution is disclosed. Only the p-type region of the silicon substrate may be selectively etched by providing means for inhibiting the injection of holes from the p-type region through the n-type region. Inhibiting the injection of holes includes forming a p-type layer over the n-type region, forming a layer of material inert to the electrochemical etchant over the n-type region, imposing a reverse electrical bias between the p-type region and n-type region, and providing recombination centers in the n-type region to induce recombination of holes injected into the n-type region.

Method for manufacturing porous semiconductor light emitting device

Abstract: An Si or SiC semiconductor layer is subjected to anodic oxidation in an HF solution to form a porous semiconductor layer. Without drying, the porous semiconductor layer is then immersed in pure water. Ultrasonic waves applied to the pure water shorten the reaction time and help bubbles separate from the surface of the porous region. The porous semiconductor layer is used for forming a pn junction, and carriers are injected into the pn junction.

A self-consistent characterization methodology for Schottky-barrier diodes and ohmic contacts

Abstract: Based on the simple interfacial-layer theory, the extraction methods for the interface parameters of the metal-semiconductor contact have been developed and applied to characterize both the Schottky-barrier diodes and the ohmic contacts in a self-consistent manner. It has been shown that the physical parameters at the metal-semiconductor interface can be extracted from the I-V characteristics of the Schottky-barrier diodes and the degradation of the thermal-equilibrium barrier height due to the thermal cycle can be directly modeled in terms of the extracted interface parameters. Besides, using the extracted parameters, the specified surface-treatment process can be evaluated by the extracted thermal-equilibrium barrier height, and thus the strongly process-dependent specific contact resistivity /spl rho//sub c/ of the ohmic contacts can be theoretically calculated by a modified tunneling model considering the impurity band. Furthermore, by comparing the simulated results and the measured /spl rho//sub c/ data deduced from the Al and Ti contacts on both doping types of the Si-substrate, satisfactory agreements have been obtained. >

Surface emitting photonic switching structure

Abstract: A surface emitting photonic switching structure includes an intermediate semiconductor structure having pn junction is sandwiched between a first semiconductor multi-layer film mirror (DBR1) and a second semiconductor multi-layer film mirror (DBR2). A pair of electrodes are provided to the intermediate semiconductor structure and the pn junction therein is applied with reverse bias voltages for changing the effective optical length of the intermediate semiconductor structure so as to change transmission wavelength of light incident on the second multi-layer film mirror or the first multi-layer film mirror. The structure can be two-dimensionally integrated, be compact and is capable of operating with low voltages.

Power transistor device having collector voltage clamped to stable level over wide temperature range

Abstract: A power transistor device is provided which has a function of clamping the collector voltage to a stable level for a wide range of temperature variations. In the power transistor device, a plurality of pn junctions are formed to fabricate Zener diodes in the polycrystalline silicon film in the form of rings. The ring configuration of the Zener diodes eliminates an end at the pn junction and prevents the junction surface from being exposed, making it possible to use as a stable Zener voltage the dielectric strength characteristic of the pn junction having a very small temperature coefficient.

Thin film transistor

Abstract: PURPOSE:To reduce the leakage current affected by gate voltage by a method wherein a clamp diode connected to gate electrodes of the thin film transistor by providing a PN junction is to be formed. CONSTITUTION:The leakage current affected by gate voltage can be reduced by a method wherein an N type polycrystalline silicon layer 4 and a P type polycrystalline silicon layer 5 are laminated on a polycrystalline silicon film 2 to be an active layer through the intermediary of a silicon oxide film 3 for patterning to form gate electrodes so that a diode may be biased in inverse direction when a gate voltage is in normal operation while the diode may be made conductive when the gate voltage is not in operation.

A model for 1/f noise in diffusion current based on surface recombination velocity fluctuations and insulator trapping

Abstract: In this paper we present a new model for low frequency 1/f noise in semiconductor diodes. The model describes noise in diffusion current due to fluctuations in surface recombination velocity. The fluctuations in surface recombination velocity are in turn caused by insulator trapping. We examine the model's predictions for 1/f noise and its dependence on device geometry, temperature, surface potential, majority carrier concentration, and trap energy. Example calculations are performed for narrow band gap HgCdTe (E/sub G/=0.125 eV at 77 K), for which this mechanism should be relevant. >

Semiconductor radiation detection apparatus for discriminating radiation having differing energy levels

Abstract: The invention provides a high sensitivity semiconductor radiation detection apparatus having pn junctions formed in opposite surfaces of at least one semiconductor wafer. A common electrode for the pn junctions is formed in the substrate region of the semiconductor wafers, and a variable reverse bias voltage is supplied to an electrode formed in contact with at least one of the pn junctions, to vary the thickness of the depletion region generated at said pn junction, and hence the sensitivity of said junction to incident radiation of varying energy levels. By adjusting the relative thickness of the respective depletion regions, different types of radiation may be distinguished.

LC element and semiconductor device

Abstract: An LC element with a pn junction layer formed near the surface of a p-Si substrate by forming an n + region having a predetermined shape and in a portion thereof additionally forming a p + region having the same shape, and with first and second electrodes formed over entire length on the surface of this pn junction layer; wherein the two electrodes respectively function as inductors and by using the pn junction layer with reverse bias, a distributed constant type capacitor is formed between these inductors, thereby providing excellent attenuation characteristics over a wide band, a semiconductor device including the LC element, and a method of manufacturing the LC element. This LC element and semiconductor device can be easily manufactured; in the case of manufacturing as a portion of an IC or LSI device, component assembly work in subsequent processing can be abbreviated, and by changing the capacitance of the distributed constant type capacitor according to requirements, the characteristics can be changed.

Microelectronic 3D bipolar magnetotransistor magnetometer

Abstract: A pyramid shaped etch is made in an n or p type silicon substrate, or any symmetric etch with slanted edges, with p or n type implants in the slanted edges of the etch to form a PN junction. On this structure, an emitter and two collectors are formed by further implanting n+ regions in the PN junction region. To complete the device, ohmic contacts are formed to establish a base region. In operation, an appropriate bias is applied to the emitter through to the base and collectors. By so biasing the device, the device operates as a standard bipolar transistor. The currents of both the minority and majority carriers in the base region will respond to the component of the magnetic field perpendicular to the face of the slanted etch. As a result, there will be a difference in the currents in the collectors. These currents can then be simply calibrated to measure the magnetic field component. By forming similar sensors on 3 or 4 of the faces of the etched structure all three components of the magnetic field can be computed.

GaAsSb-based heterojunction tunnel diodes for tandem solar cell interconnects

Abstract: We report a new approach to tunnel junctions that employs a pseudomorphic GaAsSb layer to obtain a band alignment at a InGaAs or InAlAs p-n junction favorable for forward bias tunneling. Since the majority of the band offset between GaAsSb and InGaAs or InAlAs is in the valence band, when an GaAsSb layer is placed at an InGaAs or InAlAs p-n junction the tunneling distance is reduced and the tunneling current is increased. For all doping levels studied, the presence of the GaAsSb-layer enhanced the forward tunneling characteristics. In fact, in a InGaAs/GaAsSb tunnel diode with p=1.5/spl times/10/sup 18/ cm/sup -3/ a peak tunneling current sufficient for a 1000 sun InP/InGaAs tandem solar cell interconnect was achieved while a similarly doped all-InGaAs diode was rectifying. This approach affords a new degree of freedom in designing tunnel junctions for tandem solar cell interconnects. Previously only doping levels could be varied to control the tunneling properties. Our approach relaxes the doping requirements by employing a GaAsSb-based heterojunction.

Lateral polysilicon pn diodes: current-voltage characteristics simulation between 200 K and 400 K using a numerical approach

Abstract: The current-voltage characteristics of lateral pn diodes fabricated in polysilicon layer grown by LPCVD on oxidized silicon substrates are analyzed versus temperature. The simulation proposed by Greve (1985) using the analytical current modeling is applied to forward and reverse junction currents for various temperatures; this modeling shows its limitations. Then to fit the experimental characteristics at low and high temperatures as well as at low and high current levels, a numerical modeling is developed taking into account the local electrical field effect on recombination and generation mechanisms at grain boundaries in the whole of the structure, i.e., quasi-neutral and depleted regions. This modeling allows one to fit the complete I-V experimental curves in the whole of the considered temperature range (200 K-400 K) with physical acceptable parameters. >

Stress sensitive P-N junction devices formed from porous silicon and methods for producing the same

Abstract: Stress sensitive P-N junction devices are fabricated by forming a porous layer in a semiconductor of a given conductivity, diffusing dopants of the opposite conductivity into the porous layer and forming a non-porous layer on the porous layer. This results in a microporous structure having a plurality of microcrystalline regions extending therethrough, which enhances the quantum confinement of energetic carriers and results in a device which is highly sensitive to stress.

Enhancement of oxide break-up by implantation of fluorine in poly-Si emitter contacted p/sup +/-n shallow junction formation

Abstract: In this study, it is demonstrated that the incorporation of fluorine can enhance poly-Si/Si interfacial oxide break-up in the poly-Si emitter contacted p/sup +/-n shallow junction formation. The annealing temperature for breaking up the poly-Si/Si interfacial oxide has been found to be as low as 900/spl deg/C. As a result, the junction depth of the BF/sub 2/-implanted device is much larger than that of the boron-implanted device. >

Cobalt disilicide intercell ohmic contacts for multijunction photovoltaic energy converters

Abstract: We have created thin buried films of low resistivity CoSi2 in silicon by ion implantation, and used them to provide intercell ohmic contacts for monolithically stacked multijunction photovoltaic energy converters. We have grown epitaxial silicon pn junction diodes by chemical vapor deposition onto the thin film of crystalline silicon formed over the CoSi2 layer after post‐implantation annealing. A single junction photovoltaic device with two CoSi2 contacts displayed an open circuit voltage of 0.60 V and a fill factor of 0.80, while a double junction tandem cell with three CoSi2 interconnects generated 1.2 V, under identical conditions of illumination with a Nd:YAG laser. These results indicate very low defect levels in the deposited silicon epitaxial layers, and excellent functioning of the CoSi2 interconnects.

The effects of impact ionization on the operation of neighboring devices and circuits

Abstract: This paper examines the detrimental effects of excess majority carriers and photons induced by impact ionization on the operation of neighboring pn junctions, bipolar transistors, MOS transistors, and circuits. The experimental results show that in addition to an increase in the substrate surface potential due to the excess majority carriers, photons can lower the barrier of a pn junction and, as a consequence, shift the Gummel plot of an npn bipolar transistor. As for the neighboring circuits, an example in which the speed of an NMOS ring oscillator is retarded by impact ionization in a neighboring NMOS transistor is presented. >