Showing papers on "Pass transistor logic published in 1986"

The Current Mode Fuzzy Logic Integrated Circuits Fabricated by the Standard CMOS Process

Abstract: Nine basic fuzzy logic circuits employing p-ch and n-ch current mirrors are presented, and the fuzzy information processing hardware system design at a low cost with only one kind of master slice (semicustom fuzzy logic IC) is described. The fuzzy logic circuits presented here will be indispensable for a "fuzzy computer" in the near future.

Semi-conductor integrated circuits/systems

Abstract: Configurable semiconductor integrated circuits as-made each have a plurality of logic circuits formed at discrete sites. For each logic circuit, direct selectably conducting/non-conducting connection paths extend from its output to input of a first set of other logic circuits and to its inputs from outputs of a second set of other logic circuits. All of the sets for all of the logic circuits are each different. Other direct connection paths are selectably connectable to inputs and outputs of the logic circuits. Selection can be irreversible or reversible and involves coincident signal addressing of the sites and coded configuring of the paths at that site. Reversible selection can be via field effect transistors or bipolar transistors and can be at or near normal logic signal levels and speeds. Versatile configurable input/output arrangements are described also reconfigurable data processing systems using the reversible transistor provisions.

Optical computing and the Fredkin gates

Abstract: The use of optics to implement the Boolean logic functions traditionally used in conventional electronic computing is an active area of optical computing research. Many proposed optical implementations duplicate the configuration of electronic logic gates and hence may not optimally utilize the full benefits of optical techniques. We present here a new optical gate, the Fredkin gate, which may, in principle, be minimally dissipative (i.e., exhibit reversible logic) and whose response time may be limited in some implementations only by the duration of optical pulses (i.e., in the picosecond range). Such gates, which consist of three input and three output lines, can be programmed to produce a standard set of Boolean functions and appear well matched to the parallelism of optics. We present here a number of optical implementations of Fredkin gates and suggest ways of composing their interconnections to achieve combinatorial logic, circulating memories and generalized interconnects.

Microprocessor oriented configurable logic element

Abstract: A microprocessor controlled configurable logic circuit achieves versatility by including a configurable combinational logic element, a configurable storage circuit, a configurable status buffer, and a configurable output select logic. The input signals to the configurable combinational logic element are input signals to the configurable logic circuit and feedback signals from the storage circuit. The storage circuit may be configured to operate as a D flip-flop with or without set and reset inputs, or as an edge detector. In conjunction with the combinational logic element, the storage circuit may also operate as a stage of a shift register or counter. The output select logic selects output from among the output signals of the combinational logic element and the storage circuit. The configurable status buffer may be configured to provide status information on selected important internal signals of the configurable logic circuit. A microprocessor interface structure may access an array of these configurable logic circuits through the status buffer to read different internal output signals from different circuits in the array. Providing separate input and output to a microprocessor leaves the storage element free for other uses and does not require the logic provided by the logic elements.

Design-performance trade-offs in CMOS-domino logic

Abstract: The authors present a study of the charge-sharing problem and its effect on the performance of CMOS-domino logic. Several solutions to the charge-sharing problem are examined, and the results are verified by simulation. Thus, the charge-sharing problem in CMOS-domino logic was identified and alternate approaches were evaluated.

Soft programmable logic array

Abstract: A programmable logic array is constructed of independently controllable logic building blocks of two types and special output logic to perform desired logic functions. The first building block is a functional element which is capable of performing any logical function of its input data to create output data. The functional elements shown are based on three inputs with a single output. The second basic type of building block is a pass-through/hold device which may either pass its input directly through as an output, or which may latch and hold the input until clocked. A plurality of logic levels or ranks of elements of the first type and ranks of the second type are interconnected so that the output can be various functions of the inputs. The logic array described here has first and second logic levels consisting of functional elements followed by a third level of pass-through/hold devices. The fourth and fifth logic levels are functional elements and pass-through/hold devices. The seventh and eighth logic levels are represented by another level of functional elements and pass-through/hold devices. Finally, the output logic is a plurality of output enable gates connected to tri-state buffers. The tri-state buffers may be high, low or floating. The output enable gate functions to either cause a direct pass-through of the input logic signal or activates the tri-state buffer to operate on the output logic level. The logic array is configured and controlled by input control bits to characterize the operation of each functional element and pass-through/hold device so that it functions either to produce combinations of input logic levels or to achieve particular logic states or a combination of the two functional modes. The output enable gates are controlled like the functional elements to either enable or disable tri-state control of the output buffers.

Electronic Logic Systems

Abstract: Part 1 Principles of logic systems: combinational logic logic and memory devices combinational logic at different levels of integration synchronous sequential circuits asynchronous sequential circuits arithmetic logic circuits. Part 2 Advanced logic systems: combinational logic techniques partitioning of sequential circuits partition-based design for synchronous sequential circuits partition-based design for asynchronous sequential circuits hybrid design techniques for sequential circuits CAD of logic circuits.

Concurrent fault simulation for logic designs

Abstract: A system for concurrent evaluation of the effect of multiple faults in a logic design being evaluated is particularly useful in the design of very large scale integrated circuits for developing a compact input test set which will permit locating a predetermined percentage of all theoretically possible fault conditions in the manufactured chips. The system includes logic evaluation hardware for simulating a given logic design and evaluating the complete operation thereof prior to committing the design to chip fabrication. In addition, and concurrently with the logic design evaluation, the system includes means for storing large number of predetermined fault conditions for each gate in the design, and for evaluating the "fault operation" for each fault condition for each gate, and comparing the corresponding results against the "good machine" operation, and storing the fault operation if different from the good operation. By repeating the process on an event-driven basis from gate to subsequently affected gates throughout the design, a file of all fault effects can be developed from which an input test set for the logic design can be developed based on considerations of the required percentage of all possible faults to be detected and the time that can be allowed for testing of each chip. Special hardware is provided for identifying and eliminating hyperactive or oscillating faults to maintain processing efficiency.

Sample-set differential logic (SSDL) for complex high-speed VLSI

Abstract: An improved CMOS logic circuitusing a differential cascode tree with sample and set phases of operation is presented. The sample-set differential logic (SSDL) circuit allows the use of several transistors in series in the cascode tree without significant speed degradation. Also, the signals arriving at the input require only a short valid time, which allows long interconnect delays. This improved logic circuits is compared with two other common CMOS logic circuits in a simulated design example.

Transmission-gate structured logic circuits

Abstract: Unified CMOS logic circuits are based on a structured implementation of transmission-gates. The basic logic building blocks for AND and OR circuits comprise a plurality of transmission-gates some of which may be simplified to a reduced form of a single pass transistor resulting in fewer transistors for implementing logic functions without loss of logic circuit performance characteristics. Three variable logic functions and higher order logic functions are easily implemented. Generally, the required VLSI chip area is minimized as a result of this structured transmission-gate approach.

Glitch detection by forcing the output of a simulated logic device to an undefined state

Abstract: Races and hazards in simulated logic designs are more easily detected if the logic simualtor is able to warn the designer of the presence of glitches. A glitch wall occur at the output of a logic device if an input condition causes the output to begin to change but the input condition is not present for sufficient time to allow the output to reach its stable state. The logic evaluator is the component of the logic simulator which is responsible for determining the output of a simulated device when the inputs to that device are known. The glitch detecting logic evaluator according to the present invention provides glitch detection by forcing the simulated device output to the undefined state when the device inputs change in a manner which does not allow the change to propagate to the output before a subsequent change occurs. The algorithms are designed for implementation in hardware for high performance logic simulation.

Multiple-valued threshold logic: its status and its realization

Abstract: Multiple-valued logic, in which the number of discrete logic levels is not confined to two, as is the case with all present-day digital systems, has many theoretical advantages. Multiple-valued threshold logic has particular attractions but, as with all forms of logic with more than two logic levels, is presently constrained by the lack of good devices for system realization. In this paper we introduce the theoretical attractions of multiple-valued digital systems and look toward optoelectronics for more realistic devices in the future.

Circuit simulation method with clock event suppression for debugging LSI circuits

Abstract: A computer implemented logic simulation method, for inspecting logical operations of large scale logic circuits, computes a variation of an output of at least one latch in a clock synchronized logic circuit. The clock-synchronized logic circuit contains a combination logic circuit and a plurality of logic gates. Each of the logic gates have at least one input signal and several other inputs connected to clocking signal sources of different phases. The latch is activated by the rise or fall of the clock signals for holding the output from the combination logic circuit. The method thus implements sampling instants of the output for ascertaining the logical operations of the large scale circuits.

Dual domino CMOS logic circuit, including complementary vectorization and integration

Abstract: At each stage of a domino CMOS logic circuit, the output signal S and its inversion S are separately generated in mutually complementary first and second logic networks. These outputs S and S are then used as inputs for succeeding domino logic stages. In this way, both S and S are guaranteed to be low at the end of the precharging phase as is desired for inputs to all domino logic.

CMOS programmable logic array

Abstract: A programmable logic array includes a dynamic AND plane, and an OR plane using clocked load devices. The high precharge voltage state in the AND plane places the logic lines in the OR plane in a low voltage state during precharge. The OR logic lines may then be pulled to a high level during the decode operation. A single clock having a delay path may be used to control the precharge and decode operations of the PLA.

Output buffer with improved di/dt

Abstract: An integrated circuit comprises a chip containing electric circuits in a package with leads The chip receives power via the leads The leads have inductance so that when there is a change in current flow (di/dt) through a lead there is a voltage which is developed between the end of the lead and the chip which can cause the chip to either malfunction or function poorly The highest di/dt is generally caused by an output buffer that changes the logic state of its output The typical output buffer has a pair of driver transistors that provide one of a logic high or logic low The di/dt generated by these transistors is controlled by controlling the voltage on the gate of the transistor which is providing the particular logic state This control reduces di/dt from that typically provided at the very beginning of a logic state transition but increases it over that typically provided immediately thereafter for the purpose of optimizing logic state transition speed for a given maximum di/dt

Incremental Logic Synthesis through Gate Logic Structure Identification

Abstract: This paper describes incremental logic synthesis for supporting function logic changes in the physical design stage of digital systems. The incremental logic synthesis is distinguished from logic synthesis in the respect that it updates only gate logic components, which must be changed due to the function logic changes, in the physically optimized gate logic structure. For making the incremental logic synthesis feasible, a gate logic structure identification and editing system has been developed with a corresponding gate matrix method as its core. This system has greatly contributed to the increase in design efficiency of the very large computer series M68XH.

Flyback power supply

Abstract: A flyback power supply is disclosed which includes a sample and hold feedback path. A pulse width modulation circuit provides control signals for a drive device that determines current excitation pulses for a primary winding of a transformer. A secondary winding of the transformer is connected to a rectifier circuit and provides a DC voltage signal at an output terminal. A selective feedback path is provided between the output terminal and a sense input terminal of the pulse width modulation circuit. The selective feedback path comprises a sample and hold circuit which provides for effectively coupling the output terminal to the sense input terminal at times during the storage of energy in the transformer, corresponding to an increase in transformer flux, and wherein at other times when the transformer flux is decreasing and energy is being transferred from the transformer to the rectifier circuit the feedback path effectively disconnects the output terminal from the sense input. The sample and hold circuit comprises a series pass transistor and a holding capacitor. The series pass transistor is selectively turned on and off in accordance with the control output signal of the pulse width modulation circuit that determines the primary winding current pulses.

Radiation hard gated feedback memory cell

Abstract: Pairs of cross coupled transistors are configured as a bistable regenerative circuit. Isolation means, such as diodes or transistors, are provided in the cross coupling paths to ensure that if the logic state of one transistor is temporarily changed by radiation striking the circuit, the logic state of the other transistor it is paired with will not change and the logic state of the unchanged transistor will be utilized to maintain the logic state of the other pair of transistors. CML, DTL and SDFL circuits are disclosed as the preferred embodiments.

Cmos high voltage switch

Abstract: A CMOS high voltage switch for interfacing between a decoder output and an input to an erasable, programmable read-only-memory includes an inverter for receiving an input signal from the output of the decoder. A N-channel MOS pass transistor has a conduction path and a gate electrode. One end of the conduction path is connected to the output of the inverter, and the other end of the conduction path is connected to an output node. The gate electrode of the pass transistor is connected to a first lower supply potential. A pumping device is connected to the other end of the conduction path for pumping the output node to a first higher voltage during a first mode of operation. A P-channel MOS switching transistor is also connected to the other end of the conduction path for switching the output node to a second lower voltage during a second mode of operation.

Latched domino CMOS logic

Abstract: A new gate configuration, the latched domino (Ldomino) CMOS gate, is presented. It can be used to alleviate the inversion problem inherent in domino CMOS, while improving speed and reducing layout area. Ldomino logic can serve as an efficient interface stage between blocks of static and domino or differential-cascode voltage-switch logic. The function of interfacing single-ended logic signals to differential domino-compatible logic signals is combined with the capability of efficient implementation of complex logic functions, thereby improving the logic flexibility of domino logic. A simple 4-bit ALU is used as an illustrative example of the application of Ldomino logic.

BICMOS binary logic circuits

Abstract: A BICMOS binary logic circuit or system is provided which includes P-channel and N-channel transistors, a bipolar transistor having a base connected to the drain of the P-channel transistor, a diode, preferably a Schottky barrier diode, connected between the emitter of the bipolar transistors and the drain of the N-channel transistor, a capacitor load connected to the emitter of the bipolar transistor and an input terminal connected to control electrodes of the P-channel and N-channel transistors.

MOS Pass transistor turn-off transient analysis

Abstract: Errors induced by turn-off transients are one fundamental limit in precision switched capacitor circuits. This paper presents detailed pass transistor turn-off transient analysis. Conventional single-lump models which assume quasi-static operation can introduce substantial errors for high-speed analog applications. New distributed and two-lump models have been constructed to analyze pass transistor turn-off transients in the diffusion mode of operation. A pass transistor test chip including a new selectively doped pass transistor approach has been designed, fabricated, and tested to verify the transient analysis. Measured performance of the nonuniformly doped pass transistors shows advantages in reducing transient charge errors.

SLOCOP : A Timing Verification Tool for Synchronous CMOS Logic

Abstract: In this paper, a new, accurate method for timing characterisation of synchronous CMOS circuits, described at transistor level, is presented. It is implemented in a computer program SLOCOP. SLOCOP first performs a knowledge based partitioning of the circuit into registers and combinational subcircuits, verifies high level timing rules (clock phasing) and finally detects longest signal propagation paths, with an accuracy comparable to device level simulation. Besides the delays of the critical paths, SLOCOP generates test patterns that activate these paths. The test pattern generation algorithm eliminates false paths and allows the designer to check the delay by an overall simulation. For delay calculation, local simulation is done with accurate SPICE-like transistor models. Critical paths are graphically displayed using hierarchical backannotation to a schematic. Deviations between estimated and real (simulated) delays are typically within 5% for static CMOS circuits. Pass transistor logic may give larger errors which remain however within 10%.

Programmable logic array with single clock dynamic logic

Abstract: Disclosed is a programmable logic array employing dynamic CMOS logic and utilizing a single clock signal and its complement to synchronize said dynamic logic operations. The PLA disclosed employs two logic planes for implementing arbitrary logic equations on input logic signals. The first logic plane and second logic plane are evaluated on separate phases of a clock signal and its complement and are separated by a clocked latch/inverter for providing correct logic evaluation between the logic planes.

Pulse generator circuit

Abstract: A pulse generator circuit includes (a) a delay circuit responsive to an input signal for producing an output signal after a predetermined delay time, (b) a first logic circuit responsive to the input signal and this output signal for producing an output signal having a first logic state when both of the input signal and the output signal from the delay circuit are concurrently of a second logic value, (c) a second logic circuit responsive to the input signal and the output signal from the delay circuit for producing an output signal having the first logic state when both the input signal and the output signal from the delay circuit are of the first logic value, and (d) a third logic circuit responsive to the output signal from the first logic circuit and to the output signal from the second logic circuit for producing an output signal having a first logic state when both of the output signal from the first logic circuit and the output signal from the second logic circuit are concurrently of the second logic value.

Output circuit in which induced switching noise is reduced by presetting pairs of output lines to opposite logic states

Abstract: An integrated circuit has a plurality of outputs which switch to a valid condition at the same time. Because integrated circuits have leads for power supply terminals, there is inductance on these leads. When an output switches logic states, there is a change in current flow so that there is a voltage drop across the inductive lead which is used for power supply coupling. This voltage drop, expressed Ldi/dt, is proportional to the number of outputs which are switched. The worst case for the positive power supply terminal Ldi/dt is when all of the outputs switch from a logic low to a logic high. This worst case is reduced in half by predisposing half of the outputs to one logic state and the other half to the other logic state. This also reduces the worst case for the negative power supply terminal, frequently ground, in half which is the case when all of the outputs switch from a logic high to a logic low.

Delay-time evaluation in ED MOS logic LSI

Abstract: An explicit formulation of the transient response of ED MOS logic gates is presented, including load conditions and driving waveforms. Defining delays as the time required by the current imbalance of the active inverter to charge or discharge the output load, with respect to physical reference levels, rise and fall mode delay times are obtained in an explicit formulation, with separate contributions due to fan-out and fan-in. Results are applied to ring oscillators and to depletion-load inverter chains with different configuration ratio values and are compared with SPICE simulations. With good agreement obtained, optimal structures with a low value of the configuration ratio can be defined. Analysis of propagation delay times in NOR, NAND, and transmission gates is given, allowing easy implementation of this model into logic simulators.

Test circuit for VSLI integrated circuits

Abstract: A test circuit for a VLSI integrated circuit includes interface test circuits (20) which are disposed between a logic circuit (16) an output terminal (14). The interface circuits (20) are each operable to provide a transparent interface between logic circuit (16) and output terminals (14) or force a high logic state on the output, a low logic state on the output or a floating state. A test code circuit (22) is operable to receive two logic signals from pins (24) and (26) external to the IC and determine the state of the test interface circuit (20) such that all test interface circuits (20) operate simultaneously in the same mode.

Push-pull DCFL driver circuit

Abstract: An improved driver circuit for an integrated gate circuit using Gallium Arsenide direct coupled FET logic. The push-pull driver circuit generally comprises an enhancement mode voltage follower transistor for driving a load during a first logic transition, and an enhancement mode pull-down transistor for driving this load during a second logic transition. Since only one of these transistors are conductive during these logic transitions (i.e., LO to HI, and HI to LO), little or no static current flows through these transistor means during steady state conditions. Thus, particularly for large capacitive loads, the driver circuit will be considerably faster than conventional DCFL technology, while not causing a significant increase in the power consumed by the push-pull driver circuit.