Showing papers on "Programmable logic device published in 1988"

Programmable logic device

Abstract: A programmable logic device architecture having a matrix of smaller functional units, each of which being a programmable logic array, and a set of fixed conductive lines connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection matrices. The input pins can be programmably connected to any input of any functional unit, and the outputs of functional units can be programmably connected to any input of any functional unit or any output pin. The interconnection matrices may be a simple array of crossing conductive lines with crossings connected by fuses, EPROM, or EEPROM switches or may have additional series switches to limit the effective impedance so as to speed propagation through these matrices. A fast path through one functional unit bypassing the interconnection matrices is available for a limited number of input and output pins. Multiplexers and other structures may be provided at ends of the fixed conductive lines to enable exhaustive testing of individual functional units, interconnections and logic, and structure may also be provided for on-chip monitoring of state information and providing the information to the external world when certain preselected events happen.

Optical design of programmable logic arrays.

Abstract: Regular free-space interconnects such as the perfect shuffle and banyan provided by beam splitters, lenses, and mirrors connect optical logic gates arranged in 2-D arrays. An algorithmic design technique transforms arbitrary logic equations into a near-optimal depth circuit. Analysis shows that an arbitrary interconnect makes little or no improvement in circuit depth and can even reduce throughput. Gate count is normally higher with a regular interconnect, and we show cost bounds. We conclude that regularly interconnected circuits will have a higher gate count compared with arbitrarily interconnected circuits using the design techniques presented here and that regular free-space interconnects are comparable with arbitrary interconnects in terms of circuit depth and are preferred to arbitrary interconnects for maximizing throughput.

Programmable logic array having a changeable logic structure

Abstract: Programmable Logic Array PLA) cells are arranged at intersections of input lines and output lines of the array. Particular PLA cells to be programmed are arbitrarily selected by word line and bit line decoders. Switches for programming the PLA cells to implement a desired logic function are controlled by data stored in a random access memory whereby programming of the PLA can be changed arbitrarily and during operation of a system including the PLA.

Programmable summing functions for programmable logic devices

Abstract: A programmable logic device includes a programmable logic array and an output logic macrocell The output logic macrocell includes a user configurable summing function that has a first logic gate connected to receive a first plurality of product terms, a second logic gate connected to receive a second plurality of product terms and a third logic gate connected to receive the combination of the first plurality of product terms and a controls signal, a fourth logic gate connected to receive the combination of the second plurality of Product Terms and the control signal and a logic circuit connected to receive the output signals from the first, second, third and fourth logic gates and to provide a first logical combination when the control signal is at a first logic state and a second logical combination when the controls signal is at a second logic state

Flexible, programmable cell array interconnected by a programmable switch matrix

Abstract: A high density segmented programmable array logic device utilizes a switch interconnection matrix to couple an array of programmable logic cells. Each programmable logic cell includes programmable input logic macrocells, programmable feedback logic macrocells, programmable output logic macrocells, buried state logic macrocells and an assembly of programmable AND gates and OR gates. Each input macrocell, output macrocell and buried state macrocell has means for generating either a registered/latched output signal or a combinatorial output signal in response to an input signal to the cell. The various switches are used to couple signals to or from the assembly of programmable AND gates and OR gates.

Computer Engineering: Hardware Design

Abstract: PART I. 1. Binary Numbers and Codes. 2. Digital Circuits. 3. Combinational Systems. 4. Sequential Logic. PART II. 5. Registers and Counters. 6. Memory and Programmable Logic. 7. Register Transfer and Computer Operations. 8. Control Logic Design. PART III. 9. Computer Instructions and Addressing Modes. 10. Design of a Central Processing Unit (CPU). 11. Input-Output and Communication. 12. Memory Management. Index.

Programmable logic system for filtering commands to a microprocessor

Abstract: A system utilizes one or more programmable logic arrays or gate arrays for regulating the commands available to a microprocessor, and intercepting certain of those commands according to predetermined criteria. The system selects and processes designated commands relating to the FORCE-A20 signal and CPU-RESET signal for a keyboard controller functionally attached to an INTEL 80286 or 80386 microprocessor. The system includes one or more programmable logic arrays or gate arrays for allowing all input commands to pass directly through to the keyboard controller except the command sequence relating to the FORCE-A20 signal or the CPU-RESET signal.

An architecture for electrically configurable gate arrays

Abstract: A novel architecture for CMOS electrically configurable gate arrays using a two-terminal antifuse element is described. The architecture is extensible and can provide a level of integration comparable to mask-programmable gate arrays. This is accomplished by using a conventional gate array organization with rows of logic modules separated by wiring channels. Each channel contains segmented wiring tracks. The overhead need to program the antifuses is minimized by an addressing scheme that utilizes the wiring segments, pass transistors between adjacent segments, shared control lines, and serial addressing circuitry at the periphery of the array. By providing sufficient wiring tracks segmented into carefully chosen lengths and a logic module with a high degree of symmetry, fully automated placement and routing is facilitated. >

Programmable logic device configurable input/output cell

Abstract: An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retains a particular programmed logic configuration virtually indefinitely during a powered-down state. The device is operable in a normal state and in several utility states for reconfiguring the device. The device state is controlled by an internal state machine which executes several state equations whose variables are the logic levels driving two dedicated pins and the present device state. One device pin receives serial input data which loads a shift register latch. The contents of the latch are employed to select a particular row of the cells to be programmed and the logic level to which the selected cells are to be programmed. The device normal inputs and outputs are isolated from the device during the utility states, so that the user's system does not affect the device operation during the utility states. A voltage multiplier circuit is included to generate the high voltage level necessary to program the floating gate transistors employed as the device memory cells from the device supply voltage, thereby further conserving on the required number of device pins. By programming a particular memory cell, the user may select the state of the device outputs during the utility states as either a present data latched condition or a tri-stated condition.

Implementation of iterative networks with CMOS differential logic

Abstract: An improved differential CMOS logic family called enabled/disabled CMOS differential logic (ECDL) is presented. An extension to this logic technique which enables the implementation of iterative network arrays is also presented. Two simple logic functions, a Gray-to-binary decoder and an XOR cell, are implemented to demonstrate this methodology. >

Programmable system synchronizer

Abstract: A PLL is integrated on the same chip as a programmable logic circuit and interconnected therewith in any of several useful ways. In one aspect of the invention, the output frequency of the PLL may be connected to the clock input of registers in the programmable logic circuit. If the PLL performs frequency multiplication, the chip then becomes a high-speed state machine synchronized to a lower-frequency input clock. In another aspect of the invention, the signal present at different parts of the phase lock loop may be provided to inputs of the programmable logic circuit. In another aspect, outputs of the programmable logic circuit may be used to control the operation and/or characteristics of various components in the PLL. For example, if a counter is included in the phase lock loop for causing the loop to generate a frequency multiple of the input signal, the counter may be made programmable according to outputs of the state machine. Similarly, the characteristics of the phase detector or loop filter may be dynamically adjusted according to outputs of the state machine. In yet another aspect of the invention, an output of the programmable logic circuit is, or is used to generate, one of the inputs to the phase detector in the PLL.

On the design of robust multiple fault testable CMOS combinational logic circuits

Abstract: Tests that detect modeled faults independent of the delays in the circuit under test are called robust tests. An integrated approach to the design of combinational logic circuits in which all single stuck-open faults and path delay faults are detectable by robust tests was presented by the authors earlier. It is shown that the earlier design actually results in circuits in which all multiple stuck-at and stuck-open and multipath delay faults are robustly testable. The tests to detect such faults are presented. >

A 9000-gate user-programmable gate array

Abstract: The 900-gate XC3090 CMOS user-programmable gate array is the largest member of a family of devices based on a second-generation logic cell array (LCA) architecture. This architecture features three types of user-configurable elements: an interior array of logic blocks, a perimeter of input/output (I/O) blocks, and interconnection resources. Configuration is established by programming internal static memory cells that determine the logic functions and interconnections. An IC design and layout methodology based on modularity combined with the use of advanced processing technology allowed this architecture to be extended to 9000 usable gates. Architectural resources were designed to allow for a range of logic densities without compromising overall performance. User-programmable gate arrays can be used in place of conventional, mask-programmed gate arrays for the majority of digital designs. >

In-system programmable logic device with four dedicated terminals

Abstract: An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retain a particular programmed logic configuration virtually indefinitely during a powered-down state. The device is operable in a normal state and in several utility states for reconfiguring the device. The device state is controlled by an internal state machine which executes several state equations whose variables are the logic levels driving two dedicated pins and the present device state. One device pin receives serial input data which loads a shift register latch. The contents of the latch are employed to select a particular row of the cells to be programmed and the logic level to which the selected cells are to be programmed. The device normal inputs and outputs are isolated from the device during the utility states, so that the user's system does not affect the device operation during the utility states. A voltage multiplier circuit is included to generate the high voltage level necessary to program the floating gate transistors employed as the device memory cells from the device supply voltage, thereby further conserving on the required number of device pins. By programming a particular memory cell, the user may select the state of the device outputs during the utility states as either a present data latched condition or a tri-stated condition.

Introduction to logic design

Abstract: From the Publisher: Introduction to Logic Design, Second Edition presents comprehensive discussions on analysis and design procedures and implementation schemes using popular integrated circuits...computer-aided design modules and simulation tools for conceiving and simulating programmable logic devices...the latest programmable logic concepts and devices for designing logic circuits...Simulation (Logicworks), tools that employ simulation as a logic design/verification technique...multivalued logic and field programmable gate array technologies...and more.

Implementing neural nets with programmable logic

Abstract: Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology. >

Programmable state machines connectable in a reconfiguration switching network for performing real-time data processing

Abstract: A programmable element (PE) for implementing programmable logic circuits includes a run address register, a load address register and a random access memory (RAM). The RAM is initialized with a state transition table using the load address register. After RAM initialization, and at each clock transition, the run address register is loaded with external inputs and a present state. The present state is received as the next state output of the RAM from internal feedback lines from the RAM output to the run address register inputs. The RAM output is divided into a next state which is stored in the internal feedback lines and element data outputs to an destination external to the programmable element. A state processor (SP) for implementing complex programmable logic circuits includes a plurality of programmable elements and a matrix switch. The matrix switch provides external feedback for programmable elements. In addition, any programmable output may be routed to any programmable element input. A hierarchical network of state processors for implementing programmable logic systems includes a plurality of state processors and a plurality of matrix switches. Within the hierarchical network any state processor input can receive any state processor output.

Multiple-valued logic and optimization of programmable logic arrays

Abstract: Shows a method of designing programmable logic arrays (PLAs) using multiple-valued input, two-valued output functions (MVITVOFs). A MVITVOF is an extension of the two-valued logic function. An expression for a MVITVOF directly represents a multiple-output PLA with decoders. Each product of the expression corresponds to each column of the PLA, so the number of products; in the expression equals the number of columns of the PLA. The array size of the PLA is proportional to the number of products; the PLA can thus be minimized by minimizing the expression. >

User-programmable gate arrays

Abstract: A very flexible gate array that speeds the job of designing, updating, or varying the logic circuitry that turns standard microprocessor and memory ICs into computers and peripheral equipment is examined. The gates on this kind of IC are interconnected under software control, and downloaded into local memory cells from a program written by the user, which can alter it almost at will. The array is manufactured with a grid of interconnections consisting of metal segments and programmable switching points. The user's program defines which switching points are on and which are off, and in this way groups and interconnects the gates into useful functions. On conventional gate-array ICs, the interconnections are made once and for all by the manufacturer using photolithographic masks. Various types of arrays and methods for programming them are described. The approach to designing them is discussed, highlighting differences from the process for factory-configured gate arrays. Some example applications are presented. >

Behavioral model synthesis with Cones

Abstract: The Cones synthesis system for automatic generation of VLSI implementations is discussed. Named for the cones in sequential logic, Cones takes behavioral models written in C and produces gate-level implementations in technologies such as standard cells and programmable logic arrays or programmable logic devices. The overall design is produced faster, more efficiently, and with fewer errors. Designers are free to concentrate on functions, instead of on the details of the implementation technology. >

An automated BIST approach for general sequential logic synthesis

Abstract: An automated built-in self-test (BIST) technique for general sequential logic is described. This approach has been incorporated in a behavioral model synthesis system, providing automated implementation of BIST in very-large-scale-integration (VLSI) devices as well as programmable-logic-device (PLD)-based circuit packs. BIST can be directly used at all levels of testing from device testing through system diagnostics. It is based on selective replacement of existing system memory elements with BIST flip-flop cells that are connected to form a circular chain, performing data compaction and test pattern generation simultaneously. Two production VLSI devices have been implemented with this automated BIST approach. In each case, the total fault coverage was in excess of 96% and the logic overhead incurred was between 9.7 and 18.9%. >

A 9ns Electrically Erasable Cmos Programmable Logic Device

Abstract: opment of a 9ns device t o be described, with a typical active current consumption of less than 80mA. As illustrated in Figure 1 the architecture of the device is the well-known programmable AND array, followed by a fixed OK of eight product terms per output. The Output Logic Macro Cell (OLMC) block shown on the fuse map of Figure 1 is reconfigurable via Electrically Erasable (EE) Cells to allow each output t o be programmed individually as registered or asynchronous. Polarity bits are provided for each output to select logic convention. The AND array also used EE cells, thus allowing both the logical function and the architecture to be tested during manufacturing and changed many times by the user. The gate count in the IjO path, illustrated in Figure 2, has been minimized to reduce propagation delay through the device. One area which requires special attention is the pass transistor, which follows the two-driver circuit. During cell programming, the gate of the row-pass transistor is grounded t o isolate the 16.5.V programming voltage from the high-speed, low-breakdownvoltage row-driver transistors. During normal operation, when programming voltages are removed, the row-driver circuit must drive through the NMOS-only pass transistor. To achieve a fast select time the rows must swing the full range of VSS to VCC. The gates of the pass transistors are pumped to approximately 7 V allowing the rows to go to VCC. Two levels of metalization and sub-micron channel lengths reduce propagation delays. The array has been optimized by strapping the select gate polysilicon with second metal to reduce row resistance. Two layers of metalization have allowed all speed-path interconnects to be metal, minimizing RC delays. Process and device characteristics are summarized in Tables 1 Continued process circuit enhancements have allowed devel-

On yield consideration for the design of redundant programmable logic arrays

Abstract: Redundancy techniques have been applied to conventional programmable logic arrays (PLAs) to allow for the repair of defective chips. When the redundancy technique is implemented in a VLSI or WSI chip design, the increased cost is proportional to the increased chip silicon area, and the additional spare lines can increase the silicon area and propagation delay. However, if the provided redundancy can be efficiently utilized to repair defective chip; then the additional spare lines may increase rather than decrease the chip yields. The possibility of yield enhancement through redundant design is analyzed, showing that the chip yield is increased significantly. >

An all optical programmable logic gate

Abstract: It is clear that if optical computing techniques are going to become a viable alternative to electronic techniques, they must not merely mimic electronics but provide capabilities above and beyond them. As an example of this the authors have recently demonstrated that a single nonlinear refractive bistable device can be used to provide the full adder capability (transmission providing the carry bit and reflection providing the sum bit) that requires at least five electronic gates to produce. An extension of this technique to include two coupled devices can be used to make an in-situ programmable logic gate capable of providing all eight two input Boolean functions (ON, AND, OR, XOR, NAND, NOR, XNOR, OFF) by varying holding beam power levels to each device. >

Method and apparatus for programming and verifying programmable elements in programmable devices

Abstract: A method and apparatus for programming programmable logic arrays using fewer chip resources is provided. The programmable elements in the programmable logic arrays are serially addressed using shift registers. The method and apparatus are particularly useful in conserving resources on a chip containing several programmable arrays.

Design of large embedded CMOS PLAs for built-in self-test

Abstract: A novel scheme to design built-in self-test programmable logic arrays (PLAs) implemented with CMOS technology is described, which is attractive for large arrays. These PLAs can perform function-independent self-test at normal operating speed, can detect CMOS switch-level faults, and have a lower area overhead than any other BIST scheme. A sequential parity checking technique is used to test for the AND and OR arrays of the PLA. This technique does not require any XOR cascade to evaluate parity data as in the parallel checking technique used by other schemes, thus achieving an order of magnitude reduction in total testing time. The method accounts for switch-level stuck-open and stuck-on faults in addition to conventional stuck-at, crosspoint, and bridging faults. A novel circuit design technique was used to implement the test pattern generator for product lines. It makes use of a Johnson counter and a two-level decoding network to obtain a very low area overhead and to match the pitch between the PLA and the test circuitry. >

Architecture for an improved performance of a programmable logic device

Abstract: A programmable logic device in which memory cells are removed from the signal path. Input signals are coupled to an inverting and non-inverting buffer, wherein the memory cells are coupled to enable the buffers. The stored state of each of the memory cells determines if a corresponding buffer is to be activated. In one embodiment, a memory cell is provided for each buffer and the output of each pair of complementary buffers is coupled together to provide an output. In another embodiment, the outputs of each pair of complementary buffers are inputted to a multiplexer, wherein a corresponding memory cell coupled to its multiplexer controls the selection of the signal or its complement to be outputted.

Analysis of minimization algorithms for multiple-valued programmable logic arrays

Abstract: The authors compare the performance of three heuristic algorithms for the minimization of sum-of-products expressions realized by the H.G. Kerkhoff and J.T. Butler's (1986) multiple-valued programmable logic arrays. Heuristic methods are important because exact minimization is extremely time-consuming. The authors compare the heuristics to the exact solution, showing that heuristic methods are reasonably close to minimal. They use as a basis of comparison the average number of product terms over a set of randomly generated functions. All three heuristics produce nearly the same average number of product terms. Although the averages are close, there is surprisingly little overlap among the set of functions for which the best realization is achieved. Thus, there is a benefit to applying different heuristics and then choosing the best realization. >

Programming of optical array logic. 2 : Numerical data processing based on pattern logic

Abstract: A new technique for space-variant processing with optical array logic and a new concept for parallel processing called pattern logic are proposed. Optical array logic is a technique for achieving any parallel neighborhood operation by simple coding, optical correlation, and parallel OR operation. Using pattern logic, various kinds of parallel processing can be realized, which can be implemented by optical array logic. Several kinds of numerical data processing are presented to verify the capability of pattern logic.

Emulator probe assembly for programmable logic devices

Abstract: An emulator probe assembly for testing circuit boards which control programmable logic devices includes a header assembly, a universal pod, and an extender. The header assembly includes a socket, a plug, and a flexible cable. The header socket is matched in size to the socket of the circuit board so that during testing the programmable logic device can be inserted into the header socket and the header plug into the circuit board. Some pins in the header plug are connected directly to crresponding pins in the header socket. However other pins in the header plug are connected through lines in the flexible cable to contacts in a pod plug at the opposite end of the flexible cable. Corresponding pins in the header socket are also connected through the flexible cable to contacts in the pod plug. The pod plug is received by the universal pod which has electronics for controlling or receiving signals from the programmable logic device or the circuit board. An emulator can control this universal pod to in turn control the programmable logic device and otherwise assist a designer in testing the circuit board. The extender includes test pins for applying test signals to or monitoring signals for individual pins of the programmable logic device. The extender includes removable shunts or jumpers for disconnecting certain pins in the programmable logic device from corresponding pins in the circuit board.