Showing papers on "RC circuit published in 1998"

Circuit for electrostatic discharge protection

Abstract: A circuit (100) ensures electrostatic discharge (ESD) protection during an ESD event. The ESD circuit (100) has a current shunting device (135), a RC trigger circuit (125) and a RC delay circuit (130). The shunting device (135) is connected between two IC power supply rails, and provides the primary current path for a positive ESD event referenced from one power supply rail (V DD 105) to the other (V ss 110). The trigger circuit (125) initially activates the shunting device into a low resistance conductive state in response to an ESD event. The RC delay circuit (130) serves to maintain the shunting device in the conductive state, initially produced by the trigger circuit (125), for the remaining duration of the ESD event. A large capacitor required to achieve the delay time in this RC circuit may be eliminated by utilizing the gate-to-body capacitance in the existing shunting device (135).

Cloaking circuit for use in a radio frequency identification and method of cloaking rfid tags to increase interrogation reliability

Abstract: The antenna of an RFID tag (100) is disconnected from the balance of the RFID chip by means of a series switch (24) activated in response to a logic command, CLOAK. Activation of the switch (24) disconnects the antenna (16) of the RFID tag for the remainder of the chip and effects a high impedance resistance across the antenna terminals (12, 14). An RC circuit (36, 38) is charged by activation of the CLOAK signal and thereafter discharges during a predetermined time period as determined by a high impedance series antifuse leakage transistor (34). The antenna is thus disconnected for a time sufficient to allow the remaining RFID tags to be identified.

Delay and noise formulas for capacitively coupled distributed RC lines

Abstract: Simple yet useful analytical formulas for delay, slope and crosstalk noise amplitude for capacitively coupled two-, three- and infinite-line systems are derived assuming bus lines and other signal lines in deep-submicron VLSI's. The calculated results using the derived formulas are extensively compared with SPICE simulation results to demonstrate the validity of the analytical expressions. Two modes have been studied; the case where adjacent lines are driven from the opposite direction and the case where adjacent lines are driven from the same direction. These cases correspond to the typical situations in VLSI designs and include worst cases in terms of noise amplitude and delay. Delay error in approximating the distributed RC lines by N-step /spl pi/-ladder RC lumped circuit is also investigated.

h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response

Abstract: Recently a probability interpretation of moments was proposed as a compromise between the Elmore delay and higher order moment matching for RC timing estimation (Kay and Pileggi, 1998). By modeling RC impulses as time-shifted incomplete gamma distribution function, the delays could be obtained via table lookup using a gamma integral table and the first three moments of the impulse response. However, while this approximation works well for many examples, it struggles with responses when the metal resistance becomes dominant, and produces results with impractical time shift values In this paper the probability interpretation is extended to the circuit homogeneous response, without requiring the time shift parameter. The gamma distribution is used to characterize the normalized homogeneous portion of the step response. For a generalized RC interconnect model (RC tree or mesh), the stability of the homogeneous-gamma distribution model is guaranteed. It is demonstrated that when a table model is carefully constructed, the h-gamma approximation provides for excellent improvement over the Elmore delay in terms of accuracy, with very little additional cost in terms of CPU time.

Narrowband LC folded cascode structure

Abstract: A low voltage cascode frequency conversion mixer circuit is provided. In place of a conventional current source, an LC tank circuit is used. This makes the circuit function as a mixer only over a narrow band of frequencies centred at the resonance frequency of the LC tank circuit. The circuit mixes an input signal with a local oscillator signal. Advantageously, a lower supply voltage may be used because a smaller DC drop exists across the tank circuit than does across conventional current sources. The circuit may also be used as an amplifier by connecting a DC bias voltage in place of the local oscillator.

Optimizing dominant time constant in RC circuits

Abstract: Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology, the sizing problem reduces to a convex optimization problem that can be solved using geometric programming. The tree topology restriction precludes the use of these methods in several sizing problems of significant importance to high-performance deep submicron design, including for example, circuits with loops of resistors, e.g., clock distribution meshes and circuits with coupling capacitors, e.g., buses with crosstalk between the wires. In this paper, we propose a new optimization method that can be used to address these problems. The method is based on the dominant time constant as a measure of signal propagation delay in an RC circuit instead of Elmore delay. Using this measure, sizing of any RC circuit can be cast as a convex optimization problem and solved using recently developed efficient interior-point methods for semidefinite programming. The method is applied to three important sizing problems: clerk mesh sizing and topology design, sizing of tristate buses, and sizing of bus line widths and spacings taking crosstalk into account.

Low-voltage joystick port interface

Abstract: The joystick port interface includes an integrated circuit receiving an analog joystick position measurement signal and outputting a digital pulse signal to a processor which signifies a joystick coordinate value. The integrated circuit includes a pulse generator and a bidirectional buffer circuit. The bidirectional buffer circuit receives the analog joystick position measurement signal and selectively discharges an RC network capacitor which provides this analog measurement. This implementation provides a joystick port which uses low-voltage CMOS VLSI structures which can interface a conventional high-voltage joystick with the processor.

Liquid crystal display driving circuit with low power consumption and precise voltage output

Abstract: A driving circuit for a liquid crystal display in an active matrix scheme is provided. The driving circuit comprises a multi-value voltage generating circuit, a selection circuit and an output circuit. The output circuit includes an output circuit input terminal for inputting a voltage selected by the selection circuit, a first switch connected between the output circuit input terminal and the driving circuit output terminal, a transistor having a drain connected to the first voltage source, a gate connected to the output circuit input terminal and a source connected to the driving circuit output terminal, and a second switch connected between the driving circuit output terminal and the second voltage source. During a first driving period, the driving circuit output terminal is precharged to a predetermined voltage by controlling the first switch and the second switch. During a second driving period, the transistor is operated as a source follower to output a voltage to the driving circuit output terminal. During a third driving period, the voltage of the output circuit input terminal is directly outputted to the driving circuit output terminal through the first switch.

Secondary ESD/EOS protection circuit

Abstract: To protect an input buffer from gate-oxide breakdown failure during an ESD/EOS event, an inventive secondary protection circuit is disclosed. In one embodiment, the protection circuit includes a first switch terminal connected to a pad, a second switch terminal connected to the buffer of an internal circuit, a control terminal, and an RC circuit connected between the control terminal and the supply voltage Vcc. The RC circuit delays a propagation of an ESD/EOS voltage from Vcc to the control terminal, so as to delay a generation of a conductive path between the first and second switch terminals until the ESD/EOS event lapses.

New Universal Filter with One Input and Five Outputs Using Current-Feedback Amplifiers

Abstract: A new universal voltage-mode second-order filter circuit is presented. The circuit uses five current-feedback operational amplifiers, two grounded capacitors three grounded resistors and three floating resistors. The circuit can realize all the standard filter functions; lowpass, highpass, bandpass, notch and allpass, without changing the passive elements. The proposed circuit enjoys independent grounded-resistance-control of the natural frequency and the bandwidth, low output impedances, high input impedance as well as low active and passive sensitivities.

Reduced-order modeling of large linear passive multi-terminal circuits using matrix-padé approximation

Abstract: This paper introduces SyMPVL, an algorithm for the approximation of the symmetric multi-port transfer function of an RLC circuit. The algorithm employs a symmetric block-Lanczos algorithm to reduce the original circuit matrices to a pair of typically much smaller, banded, symmetric matrices. These matrices determine a matrix-Pade approximation of the multi-port transfer function, and can serve as a reduced-order model of the original circuit. They can be ``stamped'' directly into the Jacobian matrix of a SPICE-type circuit simulator, or can be used to synthesize an equivalent smaller circuit. We also prove stability and passivity of the reduced-order models in the RL, RC, and LC special cases, and report numerical results for SyMPVL applied to example circuits.

Delay circuit and oscillator circuit using same

Abstract: Disclosed is a delay circuit for delaying at least the timing of a rising edge or the timing of a falling edge of an input signal alternating between first and second levels. The delay circuit includes (1) a charge pump in which first and second field-effect transistors of different channels are serially connected; (2) a capacitor connected in parallel with the first field-effect transistor; (3) a charging current control circuit for passing a charging current into the capacitor via the second field-effect transistor of the charge pump when the input signal is at the first level; (4) a discharge current control circuit for releasing a discharge current from the capacitor via the first field-effect transistor when the input signal is at the second level; and (5) a discrimination circuit for outputting a signal of a prescribed logic level based upon a terminal voltage of the capacitor. The values of the charging current and discharge current of the capacitor are controlled to control the slope of the input voltage to the discrimination circuit, thereby adjusting the delay time.

Converter circuit of battery charger for electric vehicle

Abstract: A battery charger converter circuit is disclosed in which a half-bridge rectifier circuit formed from two diodes, a half-bridge circuit formed from two switching elements, and a series circuit formed from two capacitors are connected at either end, respectively, thereof in parallel to each other, a boosting reactor being provided at the AC side of the half-bridge rectifier circuit; a primary circuit of the converter, including a primary coil of a high-frequency transformer, connected between a common point of connection between the switching elements and a common point of connection between the two capacitors, and a control circuit for the two switching elements; and a secondary circuit of the converter, including the secondary coil of the high-frequency transformer, a full-bridge rectifier circuit connected in parallel to the secondary coil and a smoothing capacitor; a high-frequency power generated by the primary circuit of the converter being rectified by the secondary circuit and charged into cells.

Time interval measurement system incorporating a linear ramp generation circuit

Abstract: A linear ramp generating and control circuit (10) finding particular applicability in a time interval measurement system. The linear ramp circuit includes a hold capacitor (58) which may be linearly discharged during one operating mode of the circuit by coupling a constant current source (26) to the capacitor (58). The voltage on the hold capacitor (58) is linearly discharged away from a baseline voltage level to a data voltage level which is subsequently passed to an analog-to-digital converter. The hold capacitor voltage is returned to the baseline voltage level during a recovery mode of circuit operation by a recovery or a recharge network (28). The recharge network (28) may include an active-feedback circuit which implements an approximately second order voltage response to the hold capacitor (58) during the recovery mode of operation. The circuit may also include a composite amplifier (124) for buffering the hold capacitor voltage level to a circuit output during a hold mode of circuit operation. The effect of this invention is that the errors such as drift, signal noise, and baseline voltage instability can be minimized.

Investigations on the thermal behavior of interconnects under ESD transients using a simplified thermal RC network

Abstract: This work focuses on interconnect heating during fast ESD transients. A simplified thermal RC network is used to study the behavior of interconnects and to predict their failures, which can be an open circuit or a latent failure due to the decrease in electromigration lifetime. The RC model is validated by both experiments and finite difference simulations. We observe that the melting of the interconnect system can be considered to be instantaneous. Simulations in both solid and liquid phases of the metal are in good agreement with experiments. Human body model (HBM) and machine model (MM) transients are investigated and a relationship to correlate these ESD stresses with transmission line pulse (TLP) measurements is studied in depth. We show that a square pulse of 80 ns may be used to predict HBM stress and a 45 ns pulse is proposed for MM stress.

Design and control of RC VCCS 3-D hysteresis chaos generators

Abstract: This paper proposes a simple design procedure of chaos generators consisting of two capacitors, some resistors, one linear voltage-controlled current source (VCCS), and one piecewise-linear hysteresis VCCS. The design procedure is based on nodal analysis and can guarantee the chaos generation. The resulting circuits have suitable shapes to implement on-chip and an operational transconductance amplifier (OTA) implementation example is proposed to verify the chaos generation. Also, we apply a simple control method to stabilize a desired unstable periodic orbit (UPO) embedded in chaos.

Systematic realization of low-frequency oscillators using composite passive-active resistors

Abstract: A systematic method for realizing low-frequency oscillators is described. The method is applicable to any simple harmonic oscillator configuration and is based on replacing a selected passive resistor with a composite passive-active resistor. Two possible configurations for the composite resistor are discussed. The classical Wien-bridge oscillator is then modified using one of these configurations. PSPICE circuit simulations and experimental results are included.

Switching-type DC power source apparatus

Abstract: In a switching-type DC power source apparatus which uses a booster-chopper type active filter circuit as its rectifier circuit, even at zero-crossing timing of an AC voltage to be input in the rectifier circuit, a current supply source for making a current as if it is flowing is added to a current detection circuit for detecting the current flowing in the active filter circuit, thereby preventing a prickle-like input current including a number of harmonic components from flowing in the apparatus.

Delay and power estimation for a CMOS inverter driving RC interconnect loads

Abstract: The resistive-capacitive behavior of long interconnects which are driven by CMOS gates is analyzed in this paper. The analysis is based on the /spl pi/-model of an RC load and is developed for submicron devices. Accurate and analytical expressions for the output voltage waveform, the propagation delay and the short circuit power dissipation are derived by solving the system of differential equations which describe the behavior of the circuit. The effect of the coupling capacitance between input and output and that of short circuit current are also incorporated in the proposed model. The calculated propagation delay and short circuit power dissipation are in very good agreement with SPICE simulations.

Current-Mode Active RC Filters Using Current Followers (Srecial Section on Analong Circuit Tectningues in the Digital-oriented Era)

Abstract: In this letter, a realization of current-mode active filter using current followers as active element is described. We show the constructions of second-order lowpass, highpass and bandpass filters. The high-order filters can be realized by a cascade connection of these second filters. As examples, the second-order lowpass and highpass filters are designed for frequency of 5 MHz. The effectiveness of the proposed method is demonstrated through SPICE simulation.

Controller for a vehicle starter motor

Abstract: A controller for a vehicle starter motor, the controller comprising means for applying power to the electric starter motor as a function in particular of the open or closed state of a starter switch, wherein said means include in particular an RC type circuit having a charging time constant that is shorter than its discharging time constant and that charges and discharges depending on whether the starter switch is closed or open, said control means also including means for preventing power being applied to the starter motor when the voltage across the terminals of the capacitor means of the RC circuit exceeds a given threshold.

Time-resolved breast imaging device

Abstract: A photodetection circuit for use in a laser imaging apparatus comprises a photodetector (30) adapted to respond to a laser pulse exiting from a breast being scanned; a multi-gain preamplifier circuit (40) connected to the output of the photodetector; a switch (140) connected to the output of the multi-gain preamplifier for sampling the output of the photodetector; an RC circuit (142) for spreading the sampled signal; an amplifier (142) connected to the output of the RC circuit; and an integrator (146) for integrating each sample of the output. A time-gating circuit (108) is operably connected to the switch to open and close the switch at regular intervals of time during the occurrence of the output. A laser pulse synchronization circuit (104) is operably connected to the time-gating circuit to provide a signal to the time-gating circuit as to when the laser pulse is expected to arrive at the photodetector.

Switched hybrid circuit for use with digital subscriber lines

Abstract: The present invention provides a switched impedance matching network which may be implemented in a hybrid circuit of a digital subscriber line (DSL) system, or in any other wire-bound communications system for which two-wire-to-four-wire conversion, and vice versa, must be accomplished. In accordance with the preferred embodiment of the present invention, the matching network comprises switchable circuit modules of discrete-valued resistor and capacitor components. Preferably, the circuit modules are assembled into an array of buffered first-order RC circuits. The buffers comprise amplifiers that are switched on or off to control the switching of the circuit modules. The buffer amplifiers also isolate the individual circuit modules from each other and eliminate the need to implement transmission switches between the modules. The switching of the buffer amplifiers clears or blocks the transmission paths between the individual modules, thereby providing the optimum path through the module array. By controlling the transmission paths through the circuit module array, the balancing impedance of the matching network is optimized to match the impedance of the subscriber line in use, thus maximizing transhybrid loss and minimizing near-end echo.

Valley-fill power factor correction circuit

Abstract: A valley-fill power factor correction circuit includes a rectifying circuit connected to a charge storage circuit. There is a voltage doubler circuit disposed between the rectifying circuit and the charge storage circuit. The voltage doubler circuit performs the function of filling the normally truncated input current waveform. As arranged, the input current waveform can be substantially maintained with less distortion resulting in a Fourier transform in compliance with the IEC specifications. The valley-fill circuit of the invention is capable of achieving a high power factor.

Automatic AGC bias voltage calibration in a video decoder

Abstract: A video decoder circuit is provided with automatic AGC bias voltage calibration. The video decoder circuit has an input for receiving a video signal that is capacitively coupled to an analog front-end circuit. The decoder circuit includes a microprocessor-based control circuit coupled to the analog front-end circuit. The control circuit includes a bias circuit, a gain interface circuit for changing the amplitude of the video signal prior to filtering in a filter circuit, an offset circuit for changing the DC-level shift of the video signal, and a switching circuit for switching into a calibration mode by bypassing the filter circuit and connecting the gain interface circuit directly to an analog-to-digital conversion circuit of the analog front-end circuit.

Dual coil fuel injector having smart electronic switch

Abstract: A fuel injector apparatus includes an electromagnetic fuel injector having a housing and a magnetic circuit in the housing. The magnetic circuit includes a first coil having a certain resistance to generate a peak current and a second coil having a resistance greater than the certain resistance to generate a hold current. Circuit structure is disposed in the housing and is electrically coupled with the coils to selectively excite the coils. The circuit structure includes switch structure to transition the peak current to the hold current based on a preset threshold. In a preferred embodiment of the invention, the switch structure includes an RC circuit and a comparator which sets a threshold voltage. A time constant of the RC circuit is provided to be an analog model of an inductance and resistance time constant of the fuel injector such that when a voltage of a capacitor of the RC circuit exceeds the threshold voltage, the peak current is transitioned to the hold current.

Current detection circuit and DC / DC converter provided with the current detection circuit

Abstract: PROBLEM TO BE SOLVED: To provide a circuit for detecting a current flowing into an inductor, with a small loss SOLUTION: An RC series circuit 11 is provided in parallel with an inductor L The RC series circuit 11 is constituted by a resistance Ra and a capacitor Ca connected in series each other A voltage, generated at both ends of the capacitor Ca is imparted to a detection circuit 12, and the detection circuit 12 detects an inductor current flowing through the inductor L based on the voltage When the inductance of the inductor is defined as L, the parasitic resistance value of the inductor is defined as RL, the capacity of the capacitor Ca is defined as Ca and the resistance value of the resistance Ra is defined as Ra, the RC series circuit 11 is substantially designed so as to satisfy the expression L/RL=CaRa

Generation of second-order single-OTA RC oscillators

Abstract: A direct and exhaustive method of generating canonic single-amplifier RC oscillators is introduced. Using this method, the 'complete categories' of the bandpass-based single-OTA three- and four-node RC canonic oscillators have been generated. The condition of oscillation of the resulting structures can be adjusted independently of the frequency of oscillation (FO) by the active transconductance parameter of the OTA. All the resulting oscillators enjoy low component counts. Three-node oscillators each contain only capacitors and two resistors, and the four-node oscillators each contain only two capacitors and three resistors. The sensitivities (absolute values) of the FO to the active parameter are zero and the sensitivities to the passive elements are all no greater than 1/2.

Electrostatic protection circuit of an integrated circuit

Abstract: The protection circuit of the invention connects in series with an internal circuit between a first power source and a second power source. The protection circuit includes a switch which is connected with the internal circuit and one of the first power source and a second power source; and a delay circuit which connects with the switch. The switch which is controlled by the delay circuit is closed for providing a voltage to the internal circuit in normal operation mode, and is opened when an electrostatic stress occurs.