Showing papers on "Routing (electronic design automation) published in 2002"

The impact of data aggregation in wireless sensor networks

Abstract: Sensor networks are distributed event-based systems that differ from traditional communication networks in several ways: sensor networks have severe energy constraints, redundant low-rate data, and many-to-one flows. Data-centric mechanisms that perform in-network aggregation of data are needed in this setting for energy-efficient information flow. In this paper we model data-centric routing and compare its performance with traditional end-to-end routing schemes. We examine the impact of source-destination placement and communication network density on the energy costs and delay associated with data aggregation. We show that data-centric routing offers significant performance gains across a wide range of operational scenarios. We also examine the complexity of optimal data aggregation, showing that although it is an NP-hard problem in general, there exist useful polynomial-time special cases.

A genetic algorithm for shortest path routing problem and the sizing of populations

Abstract: This paper presents a genetic algorithmic approach to the shortest path (SP) routing problem. Variable-length chromosomes (strings) and their genes (parameters) have been used for encoding the problem. The crossover operation exchanges partial chromosomes (partial routes) at positionally independent crossing sites and the mutation operation maintains the genetic diversity of the population. The proposed algorithm can cure all the infeasible chromosomes with a simple repair function. Crossover and mutation together provide a search capability that results in improved quality of solution and enhanced rate of convergence. This paper also develops a population-sizing equation that facilitates a solution with desired quality. It is based on the gambler ruin model; the equation has been further enhanced and generalized. The equation relates the size of the population, quality of solution, cardinality of the alphabet, and other parameters of the proposed algorithm. Computer simulations show that the proposed algorithm exhibits a much better quality of solution (route optimality) and a much higher rate of convergence than other algorithms. The results are relatively independent of problem types for almost all source-destination pairs. Furthermore, simulation studies emphasize the usefulness of the population-sizing equation. The equation scales to larger networks. It is felt that it can be used for determining an adequate population size in the SP routing problem.

Hermes: a distributed event-based middleware architecture

Abstract: In this paper, we argue that there is a need for an event-based middleware to build large-scale distributed systems. Existing publish/subscribe systems still have limitations compared to invocation-based middlewares. We introduce Hermes, a novel event-based distributed middleware architecture that follows a type- and attribute-based publish/subscribe model. It centres around the notion of an event type and supports features commonly known from object-oriented languages like type hierarchies and super-type subscriptions. A scalable routing algorithm using an overlay routing network is presented that avoids global broadcasts by creating rendezvous nodes. Fault-tolerance mechanisms that can cope with different kinds of failures in the middleware are integrated with the routing algorithm resulting in a scalable and robust system.

The stable paths problem and interdomain routing

Abstract: Dynamic routing protocols such as RIP and OSPF essentially implement distributed algorithms for solving the shortest paths problem. The border gateway protocol (BGP) is currently the only interdomain routing protocol deployed in the Internet. BGP does not solve a shortest paths problem since any interdomain protocol is required to allow policy-based metrics to override distance-based metrics and enable autonomous systems to independently define their routing policies with little or no global coordination. It is then natural to ask if BGP can be viewed as a distributed algorithm for solving some fundamental problem. We introduce the stable paths problem and show that BGP can be viewed as a distributed algorithm for solving this problem. Unlike a shortest path tree, such a solution does not represent a global optimum, but rather an equilibrium point in which each node is assigned its local optimum. We study the stable paths problem using a derived structure called a dispute wheel, representing conflicting routing policies at various nodes. We show that if no dispute wheel can be constructed, then there exists a unique solution for the stable paths problem. We define the simple path vector protocol (SPVP), a distributed algorithm for solving the stable paths problem. SPVP is intended to capture the dynamic behavior of BGP at an abstract level. If SPVP converges, then the resulting state corresponds to a stable paths solution. If there is no solution, then SPVP always diverges. In fact, SPVP can even diverge when a solution exists. We show that SPVP will converge to the unique solution of an instance of the stable paths problem if no dispute wheel exists.

Dynamic power consumption in Virtex™-II FPGA family

Abstract: This paper analyzes the dynamic power consumption in the fabric of Field Programmable Gate Arrays (FPGAs) by taking advantage of both simulation and measurement. Our target device is Xilinx Virtex™-II family, which contains the most recent and largest programmable fabric. We identify important resources in the FPGA architecture and obtain their utilization, using a large set of real designs. Then, using a number of representative case studies we calculate the switching activity corresponding to each resource. Finally, we combine effective capacitance of each resource with its utilization and switching activity to estimate its share of power consumption. According to our results, the power dissipation share of routing, logic and clocking resources are 60%, 16%, and 14%, respectively. Also, we concluded that dynamic power dissipation of a Virtex-II CLB is 5.9mW per MHz for typical designs, but it may vary significantly depending on the switching activity.

Tight bounds for worst-case equilibria

Abstract: The coordination ratio is a game theoretic measure that aims to reflect the price of selfish routing in a network. We show the worst-case coordination ratio on m parallel links (of possibly different speeds) isΘ(log m/log log log m)Our bound is asymptotically tight and it entirely resolves an question posed recently by Koutsoupias and Papadimitriou [3].

Cross-layer integrated collision free path routing

Abstract: A true cross-layer integration of functions is provided on several protocol layers within a network, thus providing a unified approach to Quality of Service (QoS) provisioning in a multihop network. In the unified approach, connections are preferably determined by integrated optimization of a given objective function with respect to connection parameters on at least three protocol layers within the network. Preferably, the optimization involves routing (path selection), channel access as well as adaptation of physical link parameters. By incorporating physical connection parameters together with properly designed constraints, the issue of interference can be carefully considered. It is thereby possible to determine connection parameters that ensure substantially non-interfering communication with respect to existing connections as well as the new connection.

Probabilistic location and routing

Abstract: We propose probabilistic location to enhance the performance of existing peer-to-peer location mechanisms in the case where a replica for the queried data item exists close to the query source. We introduce the attenuated Bloom filter, a lossy distributed index data structure. We describe how to use these data structures for document location and how to maintain them despite document motion. We include a detailed performance study which indicates that our algorithm performs as desired, both finding closer replicas and finding them faster than deterministic algorithms alone.

Multiple account advanced payment card and method of routing card transactions

Abstract: A system of accessing through a financial processing network multiple accounts associated with a single financial card. Data is input to the financial network in addition to the transaction data and the account identification data that in read from the card. This addition data permits the proper account to be accessed. The data may be input at the point of sale as an account selection. In this instance, the selection may be used to route the transaction data through the financial processing network or may be used to read data regarding one of multiple accounts encoded on the card. The data may also be stored as conditional routing rules at transfer points in the financial processing network. In this instance, the transaction is routed to the proper account based on the stored rules.

Wide-area content-based routing architecture

Abstract: Content networking provides a content-based routing architecture, in which a virtual overlay network called the “virtual content network” is superimposed over the physical network. The content network contains content routers as the nodes and “pathways” as links. The content-based routers at the edge of the content network may be either a gateway to the client domain or a gateway to the server domain whereas the interior ones correspond to the content switches dedicated for steering content requests and replies. The pathways are virtual paths along the physical network that connect the corresponding content routers. The tags for tagging content requests at the ingress points are designed to incorporate several different attributes of the content in the routing process. The path chosen for routing the request is the optimal path and is chosen from multiple paths leading to the replicas of the content.

Competitive routing in networks with polynomial costs

Abstract: We study a class of noncooperative general topology networks shared by N users. Each user has a given flow which it has to ship from a source to a destination. We consider a class of polynomial link cost functions adopted originally in the context of road traffic modeling, and show that these costs have appealing properties that lead to predictable and efficient network flows. In particular, we show that the Nash equilibrium is unique, and is moreover efficient. These properties make the polynomial cost structure attractive for traffic regulation and link pricing in telecommunication networks. We finally discuss the computation of the equilibrium in the special case of the affine cost structure for a topology of parallel links.

Methods, apparatuses and systems facilitating determination of network path metrics

Abstract: Methods, apparatuses and systems relating to the control and application of policies for routing data over a computer network, such as the Internet. Some implementations of the invention facilitate the configuration, deployment and/or maintenance of network routing policies. Some implementations of the invention are particularly useful for controlling the routing of data among autonomous systems or organizations. Certain implementations allow for dynamic modification of routing policy based on such factors as current Internet performance, load sharing, user-defined parameters, and time of day. In one embodiment, the present invention provides methods, apparatuses and systems implementing enhanced network path testing methodologies that enhance the efficiency of processes associated with testing of a network path, while reducing the perceived intrusiveness of test packets associated with such metrics tests.

Energy aware network management

Abstract: A method of managing a network of sensors in an energy aware manner includes the steps of clustering the sensors to minimize energy consumption, routing the network (step 44), modeling the energy available at each sensor (step 45), and re-routing the network (step 47) when the sensor battery level drops to a predetermined value, or when the energy model is adjusted because it deviates from a sensor's actual energy state.

Standard cell design incorporating phase information

Abstract: Phase information is incorporated into a cell-based design methodology Standard cells have four edges: top, bottom, left, and right The top and bottom edges have fixed phase shifters placed, eg 0 A given cell C will have a phase set created with two versions: 0-180 (left-right) as well as 180-0 Alternatively, the same phase set: 0—0 and 180—180 could be created for a cell The phase sets are selected based on the ability to phase shift the features within the cell C By creating a phase set for most of the cells of a cell library, standard cell placement and routing techniques can be used and phase can then be quickly assigned using a simple ripple technique This ensures a phase compliant design upfront for the standard cell areas In some instances, phase sets are created for every cell in a library

Content delivery network map generation using passive measurement data

Abstract: A routing method operative in a content delivery network (CDN) where the CDN includes a request routing mechanism for routing clients to subsets of edge servers within the CDN. According to the routing method, TCP connection data statistics are collected are edge servers located within a CDN region. The TCP connection data statistics are collected as connections are established between requesting clients and the CDN region and requests are serviced by those edge servers. Periodically, e.g., daily, the connection data statistics are provdied from the edge servers in a region back to the request routing mechanism. The TCP connection data statistics are then used by the request routing mechanism in subsequent routing decisions and, in particular, in the map generation processes. Thus, for example, the TCP connection data may be used to determine whether a given quality of service is being obtained by routing requesting clients to the CDN region. If not, the request routing mechanism generates a map that directs requesting clients away from the CDN region for a given time period or until the quality of service improves.

Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

Abstract: Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. This paper presents two techniques for efficient gate clustering in MTCMOS circuits by modeling the problem via Bin-Packing (BP) and Set-Partitioning (SP) techniques. An automated solution is presented, and both techniques are applied to six benchmarks to verify functionality. Both methodologies offer significant reduction in both dynamic and leakage power over previous techniques during the active and standby modes respectively. Furthermore, the SP technique takes the circuit's routing complexity into consideration which is critical for Deep Sub-Micron (DSM) implementations. Sufficient performance is achieved, while significantly reducing the overall sleep transistors' area. Results obtained indicate that our proposed techniques can achieve on average 90% savings for leakage power and 15% savings for dynamic power.

Parallel simulated annealing for the vehicle routing problem with time windows

Abstract: A parallel simulated annealing algorithm to solve the vehicle routing problem with time windows is presented. The objective is to find the best possible solutions to some well-known instances of the problem by using parallelism. The empirical evidence indicate that parallel simulated annealing can be applied with success to bicriterion optimization problems.

A new algorithm for a Dynamic Vehicle Routing Problem based on Ant Colony System

Abstract: An aboundant literature on vehicle routing problems is available. However, almost all the work deals with static problems where all data are known in advance, i.e. before the optimization has started. The technological advances of the last few years give rise to a new class of problems, namely the dynamic vehicle routing problems, where new orders are received as time progresses and must be dynamically incorporated into an evolving schedule. In this paper a dynamic vehicle routing problem is examined and a solving strategy, based on the Ant Colony System paradigm, is proposed. The method has been tested on a set of benchmarks we have defined starting from a set of widely available problems. Computational results confirm the effectiveness and the efficiency of the strategy we

Efficient circuit clustering for area and power reduction in FPGAs

Abstract: We present a routability-driven bottom-up clustering technique for area and power reduction in clustered FPGAs. This technique uses a cell connectivity metric to identify seeds for efficient clustering. Effective seed selection, coupled with an interconnect-resource aware clustering and placement, can have a favorable impact on circuit routability. It leads to better device utilization, savings in area, and reduction in power consumption. Routing area reduction of 35% is achieved over previously published results. Power dissipation simulations using a buffered pass-transistor-based FPGA interconnect model are presented. They show that our clustering technique can reduce the overall device power dissipation by an average of 13%.

Trunking inter-switch links

Abstract: A method and apparatus for routing frames through a fibre channel fabric (10) to make the most efficient possible use of redundant inter-switch links (45) between neighboring switches (45, 50). The inter-switch links (45) may have different bandwidths. The flow between adjacent switches (40, 50) is monitored to determine various local usage statistics and periodically adjust routing tables to move data flows from congested links to lightly loaded links.

System and method for hierarchical metering in a virtual router based network switch

Abstract: A virtual routing platform includes a line interface a plurality of virtual routing engines (VREs) to identify packets of different packet flows and perform a hierarchy of metering including at least first and second levels of metering on the packet flows. A first level of metering may be performed on packets of a first packet flow using a first metering control block (MCB). The first level of metering may be one level of metering in a hierarchy of metering levels. A second level of metering on the packets of the first packet flow and packets of a second flow using a second MCB. The second level of metering may be another level of metering in the hierarchy. A cache-lock may be placed on the appropriate MCB prior to performing the level of metering. The first and second MCBs may be data structures stored in a shared memory of the virtual routing platform. The cache-lock may be released after performing the level of metering using the MCB. The cache-lock may comprise setting a lock-bit of a cache line index in a cache tag store, which may identify a MCB in the cache memory. The virtual routing platform may be a multiprocessor system utilizing a shared memory having a first and second processors to perform levels of metering in parallel. In one embodiment, a virtual routing engine may be shared by a plurality of virtual router contexts running in a memory system of a CPU of the virtual routing engine. In this embodiment, the first packet flow may be associated with one virtual router context and the second packet flow is associated with a second virtual router context. The first and second routing contexts may be of a plurality of virtual router contexts resident in the virtual routing engine.

Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system

Abstract: A method for modeling integrated circuit designs in a hierarchical design automation system which utilizes a block abstraction including therein set of all database objects (cells, nets, wires, vias, and blockages) that are necessary to achieve accurate placement, routing, extraction, simulation, and verification of the block's ancestors in the hierarchy.

A Banker's solution for deadlock avoidance in FMS with flexible routing and multiresource states

Abstract: Banker's-like approaches to deadlock avoidance are based on a decision procedure to grant active processes resources using information about the maximum needs of resources that a process can request in order to ensure termination. The paper presents an extension of the classical Banker's algorithm to a class of flexible manufacturing systems modeled by means of Petri nets. These systems have two interesting characteristics from the application point of view. First, flexible routing of parts is allowed, and second, a multiset of resources is allowed to be used at each processing step. The decision procedure introduced is polynomial in the Petri net model size.

An effective congestion driven placement framework

Abstract: We present a fast but reliable way to detect routing criticalities in VLSI chips. In addition, we show how this congestion estimation can be incorporated into a partitioning based placement algorithm. Different to previous approaches, we do not rerun parts of the placement algorithm or apply a post-placement optimization, but we use our congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm. Computational experiments on chips with up to 1,300,000 cells are presented: The framework reduces the usage of the most critical routing edges by 9.0% on average, the running time increase for the placement is about 8.7%. However, due to the smaller congestion, the running time of routing tools can be decreased drastically, so the total time for placement and (global) routing is decreased by 47% on average.

Efficient method and system for automatic discovery and verification of optimal paths through a dynamic multi-point meshed overlay network

Abstract: The present invention provides an efficient system and method for routing information through a dynamic network. The system includes at least one ingress point and one egress point. The ingress and egress point cooperate to form a virtual circuit for routing packets to destination subnets directly reachable by the egress point. The egress point automatically discovers which subnets are directly accessible via its local ports and summarizes this information for the ingress point. The ingress point receives this information, compiles it into a routing table, and verifies that those subnets are best accessed by the egress point. Verification is accomplished by sending probe packets to select addresses on the subnet. Additionally, the egress point may continue to monitor the local topology and incrementally update the information to the ingress to allow the ingress to adjust its compiled routing table.

Programmable logic device structures in standard cell devices

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. A database can be expanded as new reduced logic block models are created for configurable logic block models that were not in the database. Similarly, a database can be used for the input/output blocks and programmable switch matrices of an FPGA.

The X architecture: not your father's diagonal wiring

Abstract: The X Architecture is an integrated-circuit wiring architecture based on the pervasive use of diagonal wires. Compared with the traditional, currently ubiquitous, Manhattan architecture, the X Architecture demonstrates a wire length reduction of more than 20% and a via reduction of more 30%. Because of the rapidly increasing percentage of delay due to interconnect and the manufacturing challenges due to vias in the nanometer realm, these length and via reductions result simultaneously in a chip performance improvement of 10%, a power reduction of 20%, and a die cost reduction of 30%. Furthermore, the reduction in both wire length and parallel runs on different layers often both reduces die size and improves signal integrity. Remarkably, on virtually every important measure of chip quality, the X Architecture is superior to the Manhattan architecture.While diagonal wiring has been discussed for years, and short diagonal jogs have even been used for years, pervasive diagonal wiring has not been used on an IC before 2002 (to our knowledge). The fundamental reasons for this are not manufacturing limitations, as might be suspected, but EDA limitations, and the changes required to take full advantage of the X Architecture are significant and numerous. In particular, routing must be not only octilinear, but also gridless and non-preferred direction. In addition, significant changes are required at least in floorplanning, placement, global routing, extraction, power routing, clock routing, wire length estimation (e.g., in synthesis), database, graphics, and even data interchange formats. The folklore that 45-degree wiring might not be worth the trouble because it can provide only a 10% reduction in wire length is rooted in the incorrect assumptions that (a) only the router must change, (b) the router must resemble contemporary, preferred-direction, net-at-a-time maze routers, and (c) that wire length is the only major contributor to interconnect delay.In this short paper, we present some of the challenges and opportunities afforded by the X Architecture and show some early results that demonstrate the promise of pervasive, diagonal wiring, reflecting our belief that five years from now, virtually all, high-performance, integrated circuits will use the X Architecture.

Pattern routing: use and theory for increasing predictability and avoiding coupling

Abstract: Deep submicron effects, along with increasing interconnect densities, have increased the complexity of the routing problem. Whereas previously we could focus on minimizing wirelength, we must now consider a variety of objectives during routing. For example, an increased amount of timing restrictions means that we must minimize interconnect delay. But, interconnect delay is no longer simply related to wirelength. Coupling capacitance has become a dominant component of delay due to the shrinking of device sizes. Regardless, the most important objective is producing a routable circuit. Unfortunately, this often conflicts with minimizing interconnect delay as minimum delay routes create congested areas, for which an exact routing cannot be realized without violating design rules. In this work, we use the concept of pattern routing to develop algorithms that guide the router to a solution that minimizes interconnect delay - by considering both coupling and wirelength-without damaging the routability of the circuit. The paper is divided into two parts. The first part demonstrates that pattern routing can be used without affecting the routability of the circuit. We propose two schemes to choose a set of nets to pattern route. Using these schemes, we show that the routability is not hindered. The second part builds on the previous part by presenting a framework for coupling reduction using pattern routing. We develop theory and algorithms relating pattern routing and coupling. Additionally, we give suggestions on how to extend our theory and use our algorithms for both global and detailed routing.