Showing papers on "Sequential logic published in 2007"

Modular multi-level circuits from immobilized DNA-based logic gates.

Abstract: One of the fundamental goals of molecular computing is to reproduce the tenets of digital logic, such as component modularity and hierarchical circuit design. An important step toward this goal is the creation of molecular logic gates that can be rationally wired into multi-level circuits. Here we report the design and functional characterization of a complete set of modular DNA-based Boolean logic gates (AND, OR, and AND-NOT) and further demonstrate their wiring into a three-level circuit that exhibits Boolean XOR (exclusive OR) function. The approach is based on solid-supported DNA logic gates that are designed to operate with single-stranded DNA inputs and outputs. Since the solution-phase serves as the communication medium between gates, circuit wiring can be achieved by designating the DNA output of one gate as the input to another. Solid-supported logic gates provide enhanced gate modularity versus solution-phase systems by significantly simplifying the task of choosing appropriate DNA input and output sequences used in the construction of multi-level circuits. The molecular logic gates and circuits reported here were characterized by coupling DNA outputs to a single-input REPORT gate and monitoring the resulting fluorescent output signals.

The impact of NBTI on the performance of combinational and sequential circuits

Abstract: Negative-bias-temperature-instability (NBTI) has become the primary limiting factor of circuit lifetime. In this work, we develop a general framework for analyzing the impact of NBTI on the performance of a circuit, based on various circuit parameters such as the supply voltage, temperature, and node switching activity of the signals etc. We propose an efficient method to predict the degradation of circuit performance based on circuit topology and the switching activity of the signals over long periods of time. We demonstrate our results on ISCAS benchmarks and a 65 nm industrial design. The framework is used to provide key design insights for designing reliable circuits. The key design insights that we obtain are: (1) degradation due to NBTI is most sensitive on the input patterns and the duty cycle; the difference in the delay degradation can be up to 5X for various static and dynamic conditions, (2) during dynamic operation, NBTI-induced degradation is relatively insensitive to supply voltage, but strongly dependent on temperature; (3) NBTI has marginal impact on the clock signal.

Optics inspired logic architecture

Abstract: Conventional architectures for the implementation of Boolean logic are based on a network of bistable elements assembled to realize cascades of simple Boolean logic gates. Since each such gate has two input signals and only one output signal, such architectures are fundamentally dissipative in information and energy. Their serial nature also induces a latency in the processing time. In this paper we present a new, principally non-dissipative digital logic architecture which mitigates the above impediments. Unlike traditional computing architectures, the proposed architecture involves a distributed and parallel input scheme where logical functions are evaluated at the speed of light. The system is based on digital logic vectors rather than the Boolean scalars of electronic logic. The architecture employs a novel conception of cascading which utilizes the strengths of both optics and electronics while avoiding their weaknesses. It is inherently non-dissipative, respects the linear nature of interactions in pure optics, and harnesses the control advantages of electrons without reducing the speed advantages of optics. This new logic paradigm was specially developed with optical implementation in mind. However, it is suitable for other implementations as well, including conventional electronic devices.

Combinational and sequential mapping with priority cuts

Abstract: An algorithm for technology mapping of combinational and sequential logic networks is proposed and applied to mapping into K-input lookup-tables (K-LUTs). The new algorithm avoids the hurdle of computing all K-input cuts while preserving the quality of the results, in terms of area and depth. The memory and runtime of the proposed algorithm are linear in circuit size and quite affordable even for large industrial designs. For example, computing a good quality 6-LUT mapping of an AIG with 1 M nodes takes 150 Mb of RAM and 1 minute on a typical laptop. An extension of the algorithm allows for sequential mapping, which searches the combined space of all possible mappings and retimings. This leads to an 18-22% improvement in depth with a 3-5% LOT count penalty, compared to combinational mapping followed by retiming.

Electronic Circuits: Handbook for Design and Application

Abstract: Device Models and Basic Circuits.- Diode.- Bipolar Transistor.- Field Effect Transistor.- Amplifiers.- Operational Amplifiers.- Latching Circuits.- Logic Families.- Combinatorial Circuits.- Sequential Logic Systems.- Semiconductor Memories.- General Applications.- Operational Amplifier Applications.- Controlled Sources and Impedance Converters.- Active Filters.- Signal Generators.- Power Amplifiers.- Power Supplies.- Analog Switches and Sample-and-Hold Circuits.- Digital-Analog and Analog-Digital Converters.- Digital Filters.- Measurement Circuits.- Sensors and Measurement Systems.- Electronic Controllers.- Optoelectronic Components.- Communication Circuits.- Basics.- Transmitters and Receivers.- Passive Components.- High-Frequency Amplifiers.- Mixer.

Design of Reversible Sequential Elements With Feasibility of Transistor Implementation

Abstract: This paper presents the novel designs of reversible sequential circuits (latches and flip flops). The proposed reversible latches and flip flops are designed from reversible Fredkin, Feynman and Toffoli gates. Two new reversible gates called modified Fredkin gate (MFG) and modified Toffoli gate (MTG) are also proposed to design the optimized implementations. The proposed designs are better than the recently proposed ones in terms of number of reversible gates and garbage outputs. In order to reach towards the goal of transistor implementations of proposed reversible sequential circuits, transistor implementation of the existing Feynman gate, Fredkin gate, Toffoli gates as well as the proposed MTG and MFG are also proposed. The proposed transistor implementations are completely reversible in nature, i.e., suitable for both the forward and backward computation.

Masking and Dual-Rail Logic Don't Add Up

Abstract: Masked logic styles use a random mask bit to de-correlate the power consumption of the circuit from the state of the algorithm. The effect of the random mask bit is that the circuit switches between two complementary states with a different power profile. Earlier work has shown that the mask-bit value can be estimated from the power consumption profile, and that masked logic remains susceptible to classic power attacks after only a simple filtering operation. In this contribution we will show that this conclusion also holds for masked pre-charged logic styles and for all practical implementations of masked dual-rail logic styles. Up to now, it was believed that masking and dual-rail can be combined to provide a routing-insensitive logic style. We will show that this assumption is not correct. We demonstrate that the routing imbalances can be used to detect the value of the mask bit. Simulations as well as analysis of design data from an AES chip support this conclusion.

An Analysis Framework for Transient-Error Tolerance

Abstract: Transient or soft errors are an increasing problem in mainstream microelectronics. We propose a framework for modeling transient-error tolerance (TET) in logic circuits. We classify transient errors as critical or non-critical according to their impact on circuit behavior, such as their ability to disturb the internal state for specified periods of time. We introduce a metric called the critical soft-error rate (CSER) as an alternative to conventional SER, and present some analysis strategies based on CSER. This approach employs a new single transient fault (STF) model, which is defined in terms of a temporary stuck-at fault and its associated circuit state. Although basically technology-independent, STFs can be extended with low-level physical attributes. With STFs, we can estimate the transient error probability perr of a circuit's nodes, as well as various measures of error susceptibility and TET. We demonstrate the use of STFs with combinational and sequential circuits, including several types of adders. We also present a systematic hardening strategy that uses perr as a guide to improving TET.

Soft error rate analysis for sequential circuits

Abstract: Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults (soft errors) of digital systems increases dramatically. Intensive research has been done so far in modeling and analysis of combinational circuit susceptibility to soft errors, while sequential circuits have received much less attention. In this paper, we present an approach for evaluating the susceptibility of sequential circuits to soft errors. The proposed approach uses symbolic modeling based on BDDs/ADDs and probabilistic sequential circuit analysis. The SER evaluation is demonstrated by the set of experimental results, which show that, for most of the benchmarks used, the SER decreases well below a given threshold (10-7 FIT) within ten clock cycles after the hit. The results obtained with the proposed symbolic framework are within 4% average error and up to 11000X faster when compared to HSPICE detailed circuit simulation.

A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test

Abstract: Many CAD for VLSI techniques use time-frame expansion, also known as the iterative logic array representation, to model the sequential behavior of a system Replicating industrial-size designs for many time-frames may impose impractically excessive memory requirements This work proposes a performance-driven, succinct and parametrizable quantified Boolean formula (QBF) satisfiability encoding and its hardware implementation for modeling sequential circuit behavior This encoding is then applied to three notable CAD problems, namely bounded model checking (BMC), sequential test generation and design debugging Extensive experiments on industrial circuits confirm outstanding run-time and memory gains compared to state-of-the-art techniques, promoting the use of QBF in CAD for VLSI

A Simulation Environment for e-Learning in Digital Design

Abstract: Deeds is a simulation environment for e-learning in digital electronics. The simulators cover combinational and sequential logic networks, finite state-machine design, and microcomputer interfacing and programming. They are integrated together, and therefore allow the design and test of embedded digital systems. The environment guides students' activities by delivering learning materials through specialized browsers. An extensive collection of learning materials is available. This paper includes an example of activity on a problem assignment.

Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains

Abstract: Clock skew scheduling is a technique that intentionally introduces skews to memory elements to improve the performance of a sequential circuit. It was shown in (Ravindran, 2003) that the full optimization potential of clock skew scheduling can be reliably implemented using a few skew domains. In this paper we present an optimal skew scheduling algorithm for sequential circuits with flip-flops. Given a finite set of prescribed skew domains, the algorithm finds a domain assignment for each flip-flop such that the clock period is minimized with possible delay padding. Experimental results validate the efficiency of our algorithm and show 17% improvement on average in clock period.

Using synchronization to obtain dynamic logic gates.

Abstract: We introduce a scheme to obtain key logic-gate structures, using synchronization of nonlinear systems. We demonstrate the idea explicitly by numerics and experiments on nonlinear circuits. A significant feature of this scheme is that a single nonlinear drive-response circuit can be used to flexibly yield the different logic gates, and switch logic behavior by small changes in the parameter of the response system; so the response system can act as a ``logic output controller.'' Thus this scheme may help to construct dynamic general-purpose computational hardware with reconfigurable abilities.

Automating Logic Rectification by Approximate SPFDs

Abstract: In the digital VLSI cycle, a netlist is often modified to correct design errors, perform small specification changes or implement incremental rewiring-based optimization operations. Most existing automated logic rectification tools use a small set of predefined logic transformations when they perform such modifications. This paper first shows that a small set of predefined transformations may not allow rectification to exploit the full potential of the design. Then, it proposes an automated simulation-based methodology to "approximate" sets of pairs of functions to be distinguished (SPFDs) and avoid the memory/time explosion problem. This representation is used by a SAT-based algorithm that devises appropriate logic transformations to fix a design. The SAT method is later complemented by a greedy one that improves on runtime performance. An extensive suite of experiments documents the added potential of the proposed rectification methodology.

Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions

Abstract: Boolean satisfiability is seeing increasing use as a decision procedure in electronic design automation (EDA) and other domains. Most applications encode their domain specific constraints in conjunctive normal form (CNF), which is accepted as input by most efficient contemporary SAT solvers (Moskewicz et al., 2001). However, such translation may have information loss. For example, when a circuit is encoded into CNF, structural information such as gate orientation, logic paths, signal observability, etc. is lost. However, recent research (Li, 2000) shows that a substantial amount of the lost information can be restored in circuit form. This paper presents an efficient algorithm (CNF2CKT) for extracting circuit information from CNF instances. CNF2CKT is optimal in the sense that it extracts a maximum acyclic combinational circuit from any given CNF using the logic gates pre-specified in a library. The extracted circuit structure is valuable in various ways, particularly when the CNF is not encoded from the circuit, or the circuit description is not readily available. As an example, we show that the extracted circuit structure can be used to derive circuit observability don't cares (Bartlett et al., 1988) for speeding up CNF-SAT (Fu et al., 2005)

Implementations of high throughput sequential and fully pipelined AES processors on FPGA

Abstract: In this paper, we use FPGA chips to realize the high- throughput 128 bits AES cipher processor by new high-speed and hardware sharing functional blocks. The AES functional caculations include four transformation stages, which are SubBytes, ShiftRows, MixColumns and AddRoundKey. The content-addressable memory (CAM) based scheme is used to realize the new proposed high-speed SubBytes block. The new hardware sharing architecture is applied to implement the proposed high-speed MixColumns block. Then the efficient low-cost AddRoundKey architecture is used for real-time key generations. The utilized FPGA tool is Xilinx ISEtrade 7.1 with XSTtrade synthesizer. In our proposed sequential AES design, the operational frequency can reach 75.3 MHz and the throughput can be up to 0.876 Gbits/s. In our full pipelined AES design, the operational frequency can process 250 MHz and the throughput can be up to 32 Gbits/s. Both of the proposed sequential and full pipelined AES realizations achieve higher throughput than the other sequential and full pipelined designs, individually.

Principles of Modern Digital Design

Abstract: 1. Number Systems and Binary Codes. 2. Fundamental Concepts of Digital Logic. 3. Combinational Logic Design. 4. Fundamentals of Synchronous Sequential Circuits. 5. VHDL in Digital Design. 6. Combinational Logic Design using VHDL. 7. Synchronous Sequential Circuit Design. 8. Counter Design. 9. Sequential Circuit Design using VHDL. 10. Asynchronous Sequential Circuits. Appendix A. CMOS Logic. Index.

Designing sequential transcription logic: a simple genetic circuit for conditional memory

Abstract: The ability to learn and respond to recurrent events depends on the capacity to remember transient biological signals received in the past. Moreover, it may be desirable to remember or ignore these transient signals conditioned upon other signals that are active at specific points in time or in unique environments. Here, we propose a simple genetic circuit in bacteria that is capable of conditionally memorizing a signal in the form of a tran- scription factor concentration. The circuit behaves similarly to a ''data latch'' in an electronic circuit, i.e. it reads and stores an input signal only when conditioned to do so by a ''read command.'' Our circuit is of the same size as the well-known genetic toggle switch (an unconditional latch) which consists of two mutually repressing genes, but is complemented with a ''regulatory front end'' involving protein heterodimerization as a simple way to implement conditional control. Deterministic and stochastic analysis of the circuit dynamics indicate that an experimental implementation is feasible based on well-characterized genes and proteins. It is not known, to which extent molecular networks are able to conditionally store infor- mation in natural contexts for bacteria. However, our results suggest that such sequential logic elements may be readily implemented by cells through the combination of existing protein-protein interactions and simple transcrip- tional regulation.

Complex clock gating with integrated clock gating logic cell

Abstract: Clock gating is an effective technique for minimizing dynamic power in sequential circuits. Applying clock-gating at gate-level not only saves time compared to implementing clock-gating in the RTL code but also saves power and can easily be automated in the synthesis process. This paper presents simulation results on various types of clock-gating at different hierarchical levels on a serial peripheral interface (SPI) design. In general power savings of about 30% and 36% reduction on toggle rate can be seen with different complex clock- gating methods with respect to no clock-gating in the design.

Integrated circuit including programmable logic and external-device chip-enable override control

Abstract: An integrated circuit device includes a programmable logic block, a monitoring input, a condition-sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitoring input, a first digital input, a first digital output, and a gating circuit configured in the programmable logic block and coupled between the first digital input and the first digital output. The gating circuit has a gating input coupled to the condition-sensing circuit and generates an output. The output is related to an input state of the first digital input in the absence of the condition-sensed signal and assumes an override state in the presence of the condition-sensed signal.

Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model

Abstract: Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET models to accurately capture the nonlinear properties of submicron MOS transistors. Based on these models, we propose and validate the transient pulse generation model and propagation model for soft error rate analysis. The pulse generated by our pulse generation model matches well with that of HSPICE simulation, and the pulse propagation model provides nearly one order of magnitude improvement in accuracy over the previous models. Using these two models, we propose an accurate and efficient block-based soft error rate analysis method for combinational logic circuits

DERRIC: A Tool for Unified Logic Diagnosis

Abstract: This paper presents DERRIC (Diagnosis of logic ERRors in VLSI Integrated Circuits), a diagnostic tool targeting most of the fault models used in practice today. This tool is intended to be used to diagnose faulty behaviors in nanometric circuits for which the classical stuck-at fault model is far to cover all the realistic failures. The underlying method of DERRIC is based on the Effect-Cause approach which relies on the two following main operations. The first one is based on critical path tracing (CPT) that consists in identifying critical lines in the Circuit Under Test (CUT) which can be the source of observed errors. The second one consists in allocating a set of possible fault models to each critical line, so that root causes of failures can be finally determined. The main advantage of this method is that it does not need to explicitly consider each fault model during the diagnosis process. Experiments on ISCAS'85 and ITC'99 benchmarks show the efficiency of the proposed tool in terms of diagnosis resolution.

Synthesis of Reversible Sequential Elements

Abstract: To construct a reversible sequential circuit, reversible sequential elements are required. This work presents novel designs of reversible sequential elements such as D latch, JK latch, and T latch. Based on these reversible latches, we also construct the designs of the corresponding flip-flops. Comparing with previous work, the implementation cost of our new designs, including the number of gates and the number of garbage outputs is considerably reduced.

The 3-Bit Gray Counter Based on Magnetic-Tunnel-Junction Elements

Abstract: A magnetic-tunnel-junction (MTJ) element has been widely studied for data storage applications. An MTJ element can also be used to compute Boolean functions and store the output result. A magnetologic device based on this MTJ element can constitute sequential logic functions as well as combinational logic. Counter is one of the most frequently used sequential logic blocks in digital logic systems. In this paper, a novel architecture of a 3-bit gray counter based on magnetologic elements is presented. It is shown that ten MTJ elements with complementary metal-oxide-semiconductor (CMOS) circuits for sense amplifier and writing-current driver can make a 3-bit gray counter. HSPICE simulation results are presented to verify the functionality of the proposed circuits

Error filtering in fault tolerant computing systems

Abstract: A system for tolerating a single event fault in an electronic circuit is disclosed. The system includes a main processor, a fault detection processor responsive to the main processor, the fault detection processor further comprising a voter logic circuit, three or more logic devices responsive to the fault detection processor, each output of the three or more logic devices passing through the voter logic circuit, and a programmable error filter. An output of the voter logic circuit is coupled to the programmable error filter.

Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the same

Abstract: A method of converting a Boolean logic circuit into an asynchronous multi-rail circuit is provided. A Boolean logic circuit is converted into a first multi-rail circuit using at least Shannon's expansion. The first multi-rail circuit is technology mapped into a second multi-rail circuit. Completion detection circuitry is added which receives the primary outputs of the second multi-rail circuit.

Soft Error Rate Analysis for Sequential Circuits

Abstract: Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults (soft errors) of digital systems increases dramatically. Intensive research has been done so far in modeling and analysis of combinational circuit susceptibility to soft errors, while sequential circuits have received much less attention. In this paper, we present an approach for evaluating the susceptibility of sequential circuits to soft errors. The proposed approach uses symbolic modeling based on BDDs/ADDs and probabilistic sequential circuit analysis. The SER evaluation is demonstrated by the set of experimental results, which show that, for most of the benchmarks used, the SER decreases well below a given threshold (10-7 FIT) within ten clock cycles after the hit. The results obtained with the proposed symbolic framework are within 4% average error and up to 11000X faster when compared to HSPICE detailed circuit simulation.