Showing papers on "Static induction transistor published in 1996"

Feedback loop for reading threshold voltage

Abstract: To read the threshold voltage of a transistor such as a floating gate transistor in an analog or multi-level memory cell, the transistor is connected in a feedback loop which contains a differential amplifier having an output terminal and an input terminal respectively connected to the gate and a node (source or drain) of the transistor. A reference voltage is asserted to a second input terminal of the differential amplifier. A load provides a current which charges the node, and the differential amplifier adjusts the gate voltage of the memory cell to an equilibrium value where current through the transistor is equal to current through the reference cell. The equilibrium value of the gate voltage depends on and indicates the threshold voltage of the transistor. In one embodiment of the invention, the load is a current source which mirrors a current through a reference cell that is structurally identical to the transistor, and the drain of the reference cell provides the reference voltage to the amplifier.

SOI FET design to reduce transient bipolar current

Abstract: Producing a gap between a source and/or drain region of a silicon-on-insulator (SOI) field effect transistor which is less than the thickness of a depletion region normally surrounding the source and/or drain region, preferably at zero volts bias, permits gain of a parasitic bipolar transistor formed therewith to be transiently reduced and the effective base-emitter junction capacitance to be transiently increased during only modes of operation in which the parasitic bipolar conduction dominates normal operation of the field effect transistor. Such transient reduction of gain coupled with a transient reduction of high frequency response reduces the parasitic bipolar current spike to a degree greater than previously achievable and is fully compatible with other techniques of reducing such current spike. As applied to an SOICMOS SRAM, the transistor structure including such a gap is effective in suppressing half-select write disturb effects while maintaining the benefits of excess charge storage and floating body effects in the transistor.

Semiconductor device having an insulated gate field effect thin film transistor

Abstract: A channel forming region of a thin-film transistor is covered with an electrode and wiring line that extends from a source line. As a result, the channel forming region is prevented from being illuminated with light coming from above the thin-film transistor, whereby the characteristics of the thin-film transistor can be made stable.

A brief analysis of the field effect diode and breakdown transistor

Abstract: The carrier densities of a field effect diode are calculated for the limit of a thin intrinsic silicon layer. The resulting current-voltage relation and the application of this device as a transistor are discussed. In forward bias, carrier densities can be modulated without the complications of the hot-electron effects present in regular field effect transistors. In reverse bias, it can be utilized as a transistor in which the breakdown voltage is modulated by the gate voltages.

Method for manufacturing a vertical transistor having a storage node vertical transistor

Abstract: A method for manufacturing a three-dimensionally structured vertical transistor or memory cell including the steps of forming a silicon-on-insulator (SOI) structure on a semiconductor substrate, sequentially depositing a drain region, a channel region and a source region on the SOI substrate structure, a cylinder-type gate insulation layer surrounding the channel region and a gate electrode surrounding the gate insulation layer, to thereby increase the integration of a device. This process and structure avoids the characteristic degradation caused by the leakage current associated with the trench process and structure.

DC-to-DC converter having hysteretic current limiting

Abstract: A DC-to-DC converter having hysteretic inductor current limiting and that does not have a resistor continuously carrying the inductor current. A voltage supply is coupled to a drain of a first transistor. A source of the first transistor is coupled to a first terminal of the inductor and to a drain of a second transistor. A source of the second transistor is coupled to ground through a resistor. A second terminal of the inductor is coupled to a first terminal of a capacitor. When the first transistor is on, the second transistor is off, causing current in the inductor to increase. The current flowing through the inductor charges the capacitor, and stores energy in the inductor as an increasing magnetic field. When the first transistor is off, the second transistor is on, and the stored energy is converted back into current, continuing to charge the capacitor. Voltage across the capacitor is regulated for powering a load by controlling the first and second transistors in a feedback loop. When the first transistor is off and the second transistor is on, a voltage across the resistor in series with the second transistor forms a signal representative of the inductor current. When the inductor current is higher than a first threshold at the start of a discharge cycle, the discharge cycle is extended until the inductor current falls below a second threshold, lower than the first threshold. Thus, the inductor current is hysteretically limited to prevent excessive current from damaging circuit elements.

Double balanced mixer circuit

Abstract: The present invention relates to a double-balanced mixer circuit. The double-balanced mixer circuit consists of a first differential circuit formed of a first transistor and a second transistor connected differentially to each other for receiving a first input signal; and a second differential circuit formed of a third transistor and a fourth transistor connected differentially to each other for receiving a second input signal; either the junction of the drain or collector of the first transistor and the drain or collector of the third transistor or the junction of the drain or collector of the second transistor and the drain or collector of the fourth transistor producing an output signal having frequency information on the sum of the first input signal and the second input signal or the difference between them. The double-balanced mixer circuit is used suitably as a frequency converter which is used at the high-frequency section in a mobile communications equipment such as portable telephones. The object is to handle sufficiently with a reduced voltage of the power source and to facilitate the input operation.

Semiconductor memory device having negative resistance element operated stably with single low power source

Abstract: A memory cell of an SRAM includes an access transistor, and an MIS switching diode. The access transistor has a drain electrode connected to a bit line of a corresponding column, a source electrode connected to a storage node, and a gate electrode connected to a word line of a corresponding row. The threshold voltage of the access transistor is small than the threshold voltage of a bit line load transistor. The MIS switching diode is connected between the storage node and a second power supply potential node. The switching initiate voltage of the MIS switching diode is greater than the difference between the first potential and the threshold voltage of the bit line load transistor, and smaller than the difference between the first potential and the threshold voltage of the access transistor. Thus, data can be read/written and held accurately.

Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between a well of an upper level transistor to a well of a lower transistor so as to effect direct coupling between the wells of the respective transistors. Direct coupling in this fashion affords consistent operation of transistors arranged on separate elevation levels. The via is made as short as possible so as to reduce any discrepancy in substrate/well voltage potential. This ensures predictable operation of transistors fashioned on separate elevation levels.

Multi-level transistor fabrication method with high performance drain-to-gate connection

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between the drain region of an upper level transistor to the gate of a lower level transistor so as to effect a direct coupling between the output of one transistor to the input of another. Direct coupling in this fashion affords a lower propagation delay and therefore achieves the benefit of a higher performance, faster switching circuit.

Broadband single‐electron tunneling transistor

Abstract: A single‐electron tunneling transistor has been directly coupled on‐chip to a high electron mobility transistor. The high electron mobility transistor (HEMT) is used as an impedance matching circuit with a gain close to unity. The HEMT transformed the 1.4 MΩ output impedance of the single electron tunneling (SET) transistor by two orders of magnitude down to 5 kΩ, increasing its bandwidth to 50 kHz. This circuit makes it possible to observe the motion of individual electrons at high frequencies. The requirements for the bandwidth in high frequency applications is discussed.

Level shift semiconductor device

Abstract: A level shift semiconductor device converts a signal level into another level between circuits connected to each other having different supply voltages. An input signal is supplied to the source of a first MOS transistor of a first-conductivity type (NMOS). The drain of the 1st NMOS transistor is connected to the input terminal of an inverter. An output signal is outputted via the output terminal of the inverter. The drain and gate of a first MOS transistor of a second-conductivity type (PMOS) are connected to the input and output terminals of the inverter, respectively. The gate and source of a second NMOS transistor are connected to the output terminal of the inverter and the gate of the 1st NMOS transistor, respectively. The gate and source of a second PMOS transistor are connected to the gate and source of the 2nd NMOS transistor. A first supply voltage is supplied to the drain of the 2nd PMOS transistor. And, a second supply voltage is supplied to the inverter, the source of the 1st PMOS transistor, and the drain of the 2nd NMOS transistor. The second voltage is larger in absolute value than the first voltage.

Band-switchable, low-noise voltage controlled oscillator (VCO) for use with low-q resonator elements

Abstract: Both differential and single-ended band-switchable VCOs are described. The single-ended version of the voltage controlled oscillator in its most basic form includes a load, two transistors, two delay elements, and a switchable current source. The first transistor includes a collector, an emitter and a base coupled to the load to form an output terminal for providing an oscillator output signal. The first delay element is connected between the collector and the base of the first transistor. The second transistor includes a collector, an emitter and a base connected to the base of the first transistor. The second delay element is connected between the collector of the first transistor and the collector of the second transistor. The switchable current source is connected to the emitters of the first and second transistors to provided a current to one of the transistors responsive to a control signal wherein the oscillator output signal has a first frequency of oscillation that is inversely proportional to the delay of the first transistor when the first transistor is turned on and a second frequency of oscillation inversely proportional to the sum of the first and second delay element delays when the second transistor is turned on.

Method of forming isolation regions in a MOS transistor device

Abstract: The present invention is directed to a MOS transistor and its method of fabrication. The transistor includes isolating layers below source/drain regions of the transistor. In this manner, lateral diffusion occurring in the source/drain regions can be retarded. Accordingly, the fabricated. MOS transistor has the advantages of shallow junction depth, low junction capacitance, and better punchthrough resistance. Furthermore, since the bulk of the MOS transistor might be connected to a constant voltage, most likely ground, via a contact region, the floating body effects typically encountered in SOI (silicon-on-insulator) devices can be avoided.

Lateral high-voltage DMOS transistor with drain zone charge draining

Abstract: In many circuits in which a current is switched off, a high voltage appears at the drain electrode of a transistor, in particular in the case of an inductive load. When a lateral high-voltage DMOST is used, such a high voltage may lead to instability in the transistor characteristics or may even damage the transistor. To avoid this problem, the drain of a high-voltage LDMOST is locally provided with a strongly doped n-type zone 18, 21 (in the case of an n-channel transistor) which extends, seen from the surface, down into the semiconductor body to a greater depth than does the source zone 8, so that a pn-junction is formed at a comparatively great depth in the semiconductor body having a breakdown voltage that is lower than the BV ds of the transistor without this zone. The energy stored in the inductance may thus be drained off through breakdown of the pn-junction. This breakdown is separated from the normal current path of the transistor owing to the comparatively great depth of the pn-junction, so that the robustness of the transistor is improved. This deep zone in the drain may be formed, for example, by a buried layer at the boundary between an epitaxial layer and the substrate.

High-swing cascode current mirror

Abstract: A high-swing current mirror includes a cascode current source and a current source bias circuit. The current source includes first and second bias terminals and an output terminal. The bias circuit includes transistors M1, M2A, M2B and M3A. Transistor M1 has a gate, source, and drain, with the gate coupled to the drain. Transistor M2A has a gate, source, and drain, with the gate and source of transistor M2A coupled to the gate and source, respectively, of transistor M1. Transistor M2B has a gate and drain coupled to one another and to the second bias terminal and a source coupled to the drain of transistor M2A. Transistor M3A has a gate and drain coupled together and to the first bias terminal and a source coupled to the sources of transistors M1 and M2A. The transistors in the cascode current source and current source bias circuit have ratios of device transconductance parameters such that the cascode current source remains in saturation to provide the highest possible voltage swing at the output terminal.

Method of making an ultra high density NAND gate using a stacked transistor arrangement

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allows development of a high density NAND gate. The NAND gate includes two pairs of stacked transistors, wherein one transistor of a pair can be connected to the other transistor of that pair or connected to one or both transistors of the other pair.

Power semiconductor structure with lateral transistor driven by vertical transistor

Abstract: A power semiconductor structure (200), in particular in VIPower technology, made from a chip of N-type semiconductor material (110), comprising a bipolar or field-effect vertical power transistor (125, 120, 110) having a collector or drain region in such N-type material (110); the semiconductor structure comprises a PNP bipolar lateral power transistor (210, 110, 220) having a base region in such N-type material (110) substantially in common with the collector or drain region of the vertical power transistor.

Charge pump with near zero offset current

Abstract: A charge pump of a phase-locked loop includes a first P channel transistor and a first N channel transistor coupled to mirror a current in a constant current source. The P channel transistor and N channel transistor are formed with dimensions that match transient responses of currents through the N and P channel transistors during switching rather than matching the gains of the N and P channel transistors. In one embodiment, the channel length of the N channel transistor is twice a channel length of the P channel transistor. A second P channel transistor and a second N channel transistor connected in series with the first P and N channel transistors switch the current through the first P channel transistor and the first N channel transistor respectively. The second P channel transistor and the second N channel transistor have matched gate-drain capacitances so that they have the same switching speed. A first capacitor coupled between the gate of the first P channel transistor and a supply voltage and a second capacitor coupled between the gate of the first N channel transistor and a reference voltage reduce the effect that jitter in the supply and reference voltages has on the charge pump.

Semiconductor memory device capable of operating at high speed and stably even under low power supply voltage

Abstract: A memory cell includes a read/write word line R/WL1 driving access transistor Q1 in read and write operations and a write word line WL1 driving access transistor Q2 in the write operation. In the write operation, both access transistors Q1 and Q2 are driven, and storage information is written in the memory cell by a bit line and a /bit line having potentials complementary to each other. On the other hand, in the read operation, only access transistor Q1 is rendered conductive, and storage information is read out through the bit line. Since access transistor Q2 is rendered non-conductive, a P type TFT transistor and an N type transistor operate as a CMOS type inverter having a large voltage gain. Therefore, a sufficient operating margin is secured even in the read operation.

Ultra high density NOR gate using a stacked transistor arrangement

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allow development of a high density NOR gate. The NOR gate includes two pairs of stacked transistors, wherein one transistor of a pair can be connected to the other transistor of that pair or connected to one or both transistors of the other pair.

Non-volatile memory cells using only positive charge to store data

Abstract: An improved EEPROM structure is provided which has a longer data retention period. This is achieved by utilizing only positive charges to store data on the floating gate. The EEPROM structure includes a write select transistor (112), a read select transistor (120), and a floating gate sense transistor (126). The source of the write select transistor is capacitively coupled to the floating gate of the floating gate sense transistor via a tunnel oxide layer (145). The floating gate of the floating gate sense transistor is also capacitively coupled to a control gate line (CG) via a gate oxide layer (153). The sense transistor is formed as an enhancement transistor so as to allow the EEPROM structure to be operated in a region where the floating gate potential is positive for both programmed and erased conditions, thereby using only the positive charges to store data.

Electrostatic discharge protection circuit for semiconductor device

Abstract: An ESD protection circuit (38) for a MOS device uses at least one electrically floating-base N+P-N+ transistor (43) connected between a metal bonding pad (40) and ground. The electrically floating base region (44) of each transistor is formed by a thin oxide region deposited over a substrate (50) of the MOS device. Because its N+ regions (42, 45) are made symmetrical about the floating base, each transistor conducts ESD pulses of both polarities equally. The beta of each transistor is made sufficiently large to withstand short-duration ESD current spikes. Current density is minimized by diffusing a deep N- well (54, 56) into each N+ region of each transistor to provide a larger effective conducting area. Low capacitance and higher breakdown voltage are achieved by eliminating the gate structure of prior art FET-based protection circuits.

Starting circuit and method for starting a MOS transistor

Abstract: A start up circuit causes a MOS transistor to be turned on by sensing local electrical quantities thereof, specifically the potential at the drain terminal of the MOS transistor. A small current is injected into the control terminal of the MOS transistor when the potential at the drain terminal is high. For the purpose, an electric network is arranged to couple these two terminals together.

Ultra low power pumped n-channel output buffer with self-bootstrap

Abstract: An ultra-low power pumped n-channel transistor output buffer with self-bootstrapping includes an n-channel pullup transistor as the primary pullup device. A gate-to-source capacitance C gs of the pullup transistor is used to self-bootstrap the input data signal. A pass n-channel transistor is connected between the input data signal, and the gate of the pullup transistor, and is biased on a gate terminal thereof by a charge pump having a voltage magnitude one device threshold higher than the device operating rail V cc . The pass transistor, so biased, permits the input data signal, which may have a magnitude of V cc , to charge C gs . An over-voltage can be developed on the gate of the pullup transistor by the self-bootstrapping effect of C gs . The pass transistor, in addition, so biased, prevents such over-voltage on the pullup transistors gate from being shorted to V cc through a driving device. The output buffer also includes a p-channel transistor having source and drain terminals defining a channel that is connected between another pumped voltage rail, and the gate of the pullup transistor. This p-channel transistor is activated when the output on the pad is desired to be a logic one, and operates to replenish any charge lost on the bootstrap capacitance due to leakage on the gate of the pullup transistor, or from leakage on the drain of the pass transistor. A second capacitor, similar in size to the pass transistor capacitance, is connected between the gate of the pass transistor, and the gate of a pulldown n-channel transistor, and operates to equalize and reduce the effect of transition changes in the input data signal.

Selectively grown vertical Si-p MOS transistor with short channel lengths

Abstract: Vertical p-MOS transistors with channel lengths of ~130 nm have been fabricated using selective LPCVD epitaxy for the definition of the channel region, instead of fine line lithography. Owing to self-aligned facet growth the channel region and the volume diode which limited the parasitic bipolar transistor can be designed more independently. Thus a short-channel p-MOS transistor with a high breakthrough voltage, an ideal subthreshold behaviour and a high transconductance was fabricated.

Semiconductor device and display driving device using the same

Abstract: PROBLEM TO BE SOLVED: To make a leakage current small, to perform high integration, to perform formation with less processes and to make an output level be appropriate by performing constitution by the transistors of the same conductive type. SOLUTION: The respective source and drain of P type transistors 13 and 14 are serially connected between a power source and ground, positive logic or negative logic is impressed from an input (IN) side to the gate of the P type transistor 13 and logic for which input (IN) is inverted is impressed from an inverted input (IN with upper bar) side to the gate of the P type transistor 14. Then, the source and drain of the P type transistor 12 are interposed between the inverted input (IN with upper bar) to the gate of the P type transistor 14 and a capacitor 15 whose one end is connected between the P type transistor 12 and the gate of the P type transistor 14 and other end is connected between the P type transistor 13 and connection point of the P type transistor 14 is interposed. Thus, a Low level outputted from an output terminal (OUT) is corrected so as to be a potential equivalent to a ground level.

Programmable switch matrix and method of programming

Abstract: A switch network (22) in a Field Programmable Gate Array (FPGA) which operates as a combination of a programming transistor (34) and a ferroelectric transistor (32). The programming transistor (34) is selected to transfer a polarizing voltage to a gate terminal of the ferroelectric transistor (32) for programming the ferroelectric transistor (32) in an on-state. The ferroelectric transistor (32) functions as a nonvolatile latch and pass device to provide the electrical interconnect path that links multiple Configurable Logic Blocks (CLBs). The programming transistor (34) is selected to transfer a depolarizing voltage to the gate terminal of the ferroelectric transistor (32) for programming the ferroelectric transistor (32) in an off-state.

MOS transistor structure for electro-static discharge protection circuitry

Abstract: A MOS transistor structure for an electro-static discharge (ESD) protection circuit of an integrated circuit device. The ESD protection transistor has a structure that comprises a drain diffusion region formed in the silicon substrate of the integrated circuit device, a source diffusion region formed in the silicon substrate, a gate formed in the silicon substrate, and a number of isolated islands evenly distributed throughout the drain diffusion region. The isolated islands provide substantially uniform diffusion resistance between the drain contacts and the gate while increasing the diffusion resistance of the drain region to a level suitable for ESD current protection. The disclosed MOS transistor structure may be fabricated by a salicide technology-based fabrication procedure that is completely compatible with the salicide technology used for the making of the circuitry for the IC device.

Level-shifting circuit and high-side driver including such a level-shifting circuit

Abstract: A level-shifting circuit (LSA) comprising: a series arrangement of a load resistor (RA), a main current path of an input transistor (T1A) and a bipolar series transistor (T3A) arranged as a current source and having a parasitic transistor with a small current gain factor, which is obtained, for example, by wholly surrounding the comparatively weakly doped collector region with a comparatively heavily doped material of the same conductivity type as the collector region. When the input transistor (T1A) is not conductive, a large amount of charge accumulates in the series transistor (T3A), which is then in saturation. When the input transistor (T1A) is turned on, the accumulated charge causes an overshoot in the current (IA) through the level-shifter (LSA), which overshoot compensates for the slow response as a result of the parasitic capacitance (PCA) at the node (NA).