Showing papers on "System bus published in 2002"

Systems and methods for multiple mode voice and data communications using intelligenty bridged TDM and packet buses and methods for performing telephony and data functions using the same

Abstract: Systems and methods by which voice/data communications may occur in multiple modes/protocols are disclosed. In particular, systems and methods are provided for multiple native mode/protocol voice and data transmissions and receptions with a computing system having a multi-bus structure, including, for example, a TDM bus and a packet bus, and multi-protocol framing engines. Such systems preferably include subsystem functions such as PBX, voice mail and other telephony functions, LAN hub and data router. In preferred embodiments, a TDM bus and a packet bus are intelligently bridged and managed, thereby enabling such multiple mode/protocol voice and data transmissions to be intelligently managed and controlled with a single, integrated system. A computer or other processor includes a local area network controller, which provides routing and hub(s) for one or more packet networks. The computer also is coupled to a buffer/framer, which serves to frame/deframe data to/from the computer from TDM bus. The buffer/framer includes a plurality of framer/deframer engines, supporting, for example, ATM and HDLC framing/deframing. The buffer/framer is coupled to the TDM bus by way of a switch/multiplexer, which includes the capability to intelligently map data traffic between the buffer/framer and the TDM bus to various slots of the TDM frames. Preferably, a DSP pool is coupled to buffer/framer in a manner to provide various signal processing and telecommunications support, such as dial tone generation, DTMF detection and the like. The TDM bus is coupled to a various line/station cards, serving to interface the TDM bus with telephone, facsimiles and other telecommunication devices, and also with a various digital and/or analog WAN network services.

Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity

Abstract: An internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity. The bus system can transmit data between a plurality of function blocks, where multiple data packets can be on the bus at the same time. The bus system automatically recognizes the correct connection for various types of data or data transmitters and sets it up.

Memory controller for multilevel cell memory

Abstract: A N-level cell memory controlled by the memory controller of the invention have an internal configuration in which the plurality of data input/output terminals connected to the second data bus are separated into first through Mth data input/output terminal groups, such that there is no redundancy in the n bits of data associated with one N-level cell. Together with this, the memory controller separates the plurality of data bits on the first data bus into first through Mth data groups, the ECC circuits generate error-correction codes for each of these data groups, and the first through Mth data groups and first through Mth error correction codes are input to the first through Mth data input/output terminals of the N-level cell memory, via the second data bus.

Semiconductor memory device having multi-bit testing function

Abstract: In a multi-bit test, an I/O combiner degenerates data of a plurality of bits read from a memory cell array to first to fourth data bus pairs in parallel and outputs the degenerated data to a fifth data bus. A read amplifier compares a logic level of the degenerated data received from the I/O combiner with a logic level of expected value data. If the logic level of the degenerated data coincides with the logic level of the expected value data, the read amplifier determines that data write and read to and from the plurality of bits have been normally performed. As a result, a semiconductor memory device can detect a word line defect in the multi-bit test.

Vehicle tracking unit for controlling operable vehicle devices using a vehicle data bus and related methods

Abstract: A vehicle tracking unit is provided for a vehicle of a type comprising a vehicle data bus extending throughout the vehicle and at least one operable vehicle device connected thereto. The at least one operable vehicle device may be responsive to at least one data bus code on the vehicle data bus. The vehicle tracking unit may include a vehicle position determining device, a wireless communications device, and a controller cooperating with the vehicle position determining device and the wireless communications device to send vehicle position information to a monitoring station. Moreover, the controller may generate the at least one data bus code on the vehicle data communications bus to control the at least one operable vehicle device based upon a command signal received by the wireless device.

Apparatus and method for awakening bus circuitry from a low power state

Abstract: Apparatus and techniques for awakening bus circuitry from an inactive state as needed are described. The bus circuitry forms part of a computer system and is placed in the inactive state (i.e., shut down) when not needed so as to conserve power. The bus circuitry is associated with a bus and can be awakened out of the inactive state when certain bus events, including resume, connect or disconnect, occur on the bus. The invention is particularly advantageous for computing devices (e.g., portable computers, desktop computers, server computers) where it is desirous to shut down bus circuitry as well as other circuitry (e.g., microprocessor) when not needed so as to reduce power consumption.

Apparatus and method for controlling data transmission

Abstract: An interface for controlling the transmission of data between integrated circuit (IC) chips. The interface comprises a data bus for transmitting data from a first integrated circuit chip to a second integrated circuit chip, and a control bus for transmitting control signals between the first and second integrated circuits. The first IC has a memory for receiving data for transmission to the second IC, and the second IC has a scheduler and a data output port, the scheduler being arranged to control the transfer of data from the memory of the first IC to the data output port of the second IC via the data bus. The interface is capable of stopping and reinitiating data transmission on detection of errors in transmitted data, and the interface may include a code transfer bus for transferring error detection code separately from associated data.

Logging insertion/removal of server blades in a data processing system

Abstract: This invention is comprised of a data processing system containing at least one main processor connected to a system bus, a system memory connected to the system bus and accessible to each of the main processors, a tamper mechanism, and a local service processor. The tamper mechanism is configured to change state each time the system is inserted into a slot in a rack enclosure. The local service processor is connected to the tamper mechanism and configured to update an insertion log upon detecting a change in state of the tamper mechanism. The insertion log provides a count and a history of rack insertions to which the system has been subjected. The system may include a non-volatile storage element which is updated exclusively by the local service processor that contains the insertion log. The insertion log may include an insertion counter. In this embodiment, the local service processor is configured to increment the insertion counter upon each insertion. The local service processor may be further configured to issue an alert if the insertion counter exceeds a predetermined value. In one embodiment, the system further includes a battery backed real-time clock connected to the local service processor. The local service processor is configured to include real-time information corresponding to each insertion event in the insertion log. Each entry in the insertion log may include the identity of the rack enclosure and the geographical address of the slot of the corresponding insertion event. The local service processor may be configured to detect the tamper mechanism state and update the insertion following a power event such that the insertion log update is independent of configuring the data processing system with a boot image.

Bus control system

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Systems and methods for multiple mode voice and data communications using intelligently bridged TDM and packet buses

Abstract: Systems and methods by which voice/data communications may occur in multiple modes/protocols are disclosed. In particular, systems and methods are provided for multiple native mode/protocol voice and data transmissions and receptions with a computing system having a multi-bus structure, including, for example, a TDM bus and a packet bus, and multi-protocol framing engines. Such systems preferably include subsystem functions such as PBX, voice mail and other telephony functions, LAN hub and data router. In preferred embodiments, a TDM bus and a packet bus are intelligently bridged and managed, thereby enabling such multiple mode/protocol voice and data transmissions to be intelligently managed and controlled with a single, integrated system. A computer or other processor includes a local area network controller, which provides routing and hub(s) for one or more packet networks. The computer also is coupled to a buffer/framer, which serves to frame/deframe data to/from the computer from TDM bus. The buffer/framer includes a plurality of framer/deframer engines, supporting, for example, ATM and HDLC framing/deframing. The buffer/framer is coupled to the TDM bus by way of a switch/multiplexer, which includes the capability to intelligently map data traffic between the buffer/framer and the TDM bus to various slots of the TDM frames. Preferably, a DSP pool is coupled to buffer/framer in a manner to provide various signal processing and telecommunications support, such as dial tone generation, DTMF detection and the like. The TDM bus is coupled to a various line/station cards, serving to interface the TDM bus with telephone, facsimiles and other telecommunication devices, and also with a various digital and/or analog WAN network services.

Torque estimator for engine RPM and torque control

Abstract: An engine toque estimator according to the invention includes a vehicle data bus that provides a plurality of engine operating inputs including at least one of engine RPM, spark and a dilution estimate. A steady state torque estimator communicates with the vehicle data bus and generates a steady state engine torque signal. A measurement model communicates with the vehicle data bus and compensates for errors associated with engine-to-engine variation. A dynamic torque estimator communicates with at least one of the vehicle data bus, the measurement model, and the steady state torque estimator and generates an actual torque signal.

Integrated gigabit ethernet PCI-X controller

Abstract: A network controller having a multiprotocol bus interface adapter coupled between a communication network and a computer bus, the adapter including a predictive time base generator; and a management bus controller adapted to monitor and manage preselected components coupled with one of the communication network and the computer bus. The management bus controller is adapted to employ an Alert Standard Format (ASF) specification protocol, a System Management Bus (SMBus) specification protocol, an Intelligent Platform Management Interface (IPMI) specification protocol, a Simple Network Management Protocol (SNMP), or a combination thereof. The network controller also includes a 10/100/1000BASE-T IEEE Std. 802.3-compliant transceiver and media access controller coupled with the communication network; a buffer memory coupled with the MAC, wherein the buffer memory includes one of a packet buffer memory, a frame buffer memory, a queue memory, and a combination thereof; and a transmit CPU and a receive CPU coupled with the multiprotocol bus interface adapter and the management bus controller. The network controller can be a single-chip VLSI device in an 0.18 micron CMOS VLSI implementation.

High speed bus interface for non-volatile integrated circuit memory supporting continuous transfer

Abstract: An apparatus is described, comprising a plurality of banks, each bank having a number of columns of non-volatile storage units, each non-volatile storage unit having an input buffer for storing a page of data, the page having an input coupled to the input buffer accepting an input portion of data of a page at a memory speed, the non-volatile storage units storing the data from the input buffer within a memory write time; a plurality of interface buffers; an input bus having an input bus speed which is faster than the memory speed, the input bus being coupled to the plurality of interface buffers; a bus system, connecting each of the plurality of interface buffers to the non-volatile storage units of a column in each of the plurality of banks, supplying data from the plurality of interface buffers to the inputs of the non-volatile storage units at the memory speed.

Memory module including module data wirings available as a memory access data bus

Abstract: A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each individual memory modules are connected in serial form, and each individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.

Method and Apparatus for Distributed Direct Memory Access for Systems on Chip

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Method and system for supporting multiple bus protocols on a set of wirelines

Abstract: A universal bus communicates information by one of plural bus protocols. A bus protocol selector is operable to select one of the plural bus protocols associated with a device interfaced with an information handling system and to communicate information over the bus with the selected bus protocol. An Input/Output chip includes a protocol selector unit that selects a bus protocol I/O unit to communicate with the device over the universal bus. The bus protocol I/O unit communicates over the universal bus by using a bus protocol that is compatible with the device. For instance, the one of plural available differential serial bus protocols is selected so that the bus protocol I/O unit communicates with the device using a bus protocol compatible with the device. In some instances, a bypass circuit configures the physical characteristics of the universal bus, such as by interfacing or removing a capacitor with the universal bus to support AC or DC coupled bus protocols.

Memory system having point-to-point bus configuration

Abstract: A clocking system and method in a point-to-point bus configuration overcomes the limitations of conventional approaches. In one embodiment, the present invention ensures the same phase relationship for the write clock in the write direction for all data transfers between modules, and similarly the same phase relationship for the read clock in the read direction for all data transfers between modules, regardless of module location. In another embodiment, on a given module, all transfers of data between a data buffer and a memory device in both read and write directions are clocked by a read clock signal and a write clock signal that have the same phase relationship and have the same propagation delay as the data bus between the buffer and the memory device.

Serial bus control method and apparatus for a microelectronic power regulation system

Abstract: A serial bus control method, apparatus, and system for transmitting signals between a master controller and a slave controller associated with a power regulator are disclosed. The serial bus control scheme allows for information to be written to or read from individual regulators or to be written to or read from all regulators that are coupled to the master controller.

Network to computer internal interface

Abstract: An apparatus for connecting a computer bus to a network comprises a network interface capable of coupling to an external network and an emulator coupled to the network interface. The emulator comprises a processor control block that can emulate a host processor coupled to the computer bus and a device control block that can emulate a device coupled to the computer bus.

Automated Bus Generation for Multiprocessor SoC Design

Abstract: The performance of a multiprocessor system heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custom bus system for a multiprocessor system-on-a-chip (SoC). Our bus-synthesis tool, which we call BusSynth, uses this methodology to generate five different bus systems as examples: 1) bidirectional first-in first-out bus architecture; 2) global bus architecture (GBA) version I; 3) GBA version III; 4) hybrid bus architecture (Hybrid); and 5) split bus architecture. We verify and evaluate the performance of each bus system in the context of three applications: an orthogonal frequency division multiplexing wireless transmitter, an MPEG2 decoder, and a database example. Our methodology gives the designer a great benefit in the fast-design space exploration of bus architectures across a variety of performance impacting factors such as bus types, processor types, and software programming style. In this paper, we show that BusSynth can generate buses that, when compared to a typical general GBA, achieve superior performance (e.g., 41% reduction in execution time in the case of a database example). In addition, the bus architecture generated by BusSynth is designed in a matter of seconds instead of weeks for the hand design of a custom bus system.

Memory control system

Abstract: The processor, upon fetching a sleep command, stops its own operation and outputs an internal power-down signal The power-down control circuit outputs, upon receiving the internal power-down signal from the processor, a control signal to put a volatile semiconductor memory connected to the system bus into a self refresh mode Thus, the processor can simply fetch the sleep command to put the semiconductor memory into the self refresh mode Since system programs need not include any processing program for putting the semiconductor memory into the self refresh mode, the software processing can be prevented from being complicated As a result, it is possible to reduce the burden on the program developers

Memory device and memory system

Abstract: In a memory device which is used with the memory device connected to a data bus, the memory device includes an active termination circuit for terminating the memory device when the active termination circuit is electrically put into an active state and for unterminating the memory device when the active termination circuit is electrically put into an inactive state. The memory device further includes a control circuit for controlling the active termination circuit to electrically put the active termination circuit into the active state or the inactive state.

Microprocessor with integrated interfaces to system memory and multiplexed input/output bus

Abstract: A single-chip IC device has an on-board CPU, an I/O bus controller, and a memory controller all implemented in semiconductor devices on the chip. The CPU, I/O bus controller, and memory controller are interconnected on the IC chip by a parallel data and address bus formed by the IC manufacturing techniques of deposition, patterning, and etching. In a preferred embodiment the on-board local bus has 32 address and 32 data lines. Also in a preferred embodiment the I/O bus controller has 32 data and address paths off the die for connection to a multiplexed I/O bus. The memory controller in the same embodiment has 32 data and 11 address paths off the die to a memory bus with 43 data and address lines. The I/O bus controller is configured to rout memory requests from peripheral devices through the memory controller directly to system memory.

Fringe field switching liquid crystal display device and method for manufacturing the same

Abstract: The present invention comprises an upper substrate; a data bus line and a storage capacitance bus line on a lower substrate; a gate bus line at the position of bisecting the unit pixel; a thin film transistor on the gate bus line; a counter electrode; and a pixel electrode. The pixel electrode comprises a frame shaped body unit formed on the edge in counter electrode and a plurality of slant slits arranged with a regular distance to divide the body unit into several parts, forming a predetermined angle with the gate bus line. The angle of slant slits in the pixel electrode is symmetric with respect to the gate bus line. The storage capacitance bus line is partially overlapped with both the upper edge of pixel electrode in one unit pixel and the lower edge of pixel electrode in the closest unit pixel. According to the present invention, the black matrix area is reduced by eliminating or minimizing the light leakage through modifying the pixel structure, thereby improving the aperture ration and transmittance.

Digital signal processor for wireless baseband processing

Abstract: A circuit employing an array of reconfigurable.processing elements for wireless baseband processing. The circuit includes a first linear array of reconfigurable processing elements for processing signals from a first channel, and a second linear array of reconfigurable processing elements, coupled in parallel with the first linear array of reconfigurable processing elements, for processing signals from a second channel that is concurrent with the first channel. The circuit also includes a frame buffer array having a number of frame buffers that corresponds to a number of reconfigurable processing elements in the first and second linear arrays of processing elements. A point-to-point data bus is connected between each reconfigurable processor and an associated frame buffer. A shared data bus is connected between the first and second linear arrays of reconfigurable processing elements and the frame buffer array.

Image display device

Abstract: PROBLEM TO BE SOLVED: To reduce the data bus occupation rate of an image layer memory by eliminating unnecessary repeated execution of the same composing operation even in the case that a display frame is not updated at display of a multi-layer picture SOLUTION: A frame update flag 110 indicating whether the display frame has been updated or not for each frame and an update frequency flag 111 indicating whether a low frequency mode in which the update frequency of the display frame is lower than a reference value is set or not are provided When the low frequency mode is set and the frame update flag 110 indicates that the display frame has been updated, a plurality of image layers 101 to 104 are successively read out from the picture layer memory 100 to generate a composite picture, and this image is not only preserved in the image layer memory 100 as a composite layer but also supplied to a display monitor 117 When the low frequency mode is set and the frame update flag 110 indicates that the display frame has been not updated, the preserved composite layer 105 is read out and supplied to the display monitor 117

System and method of mastering a serial bus

Abstract: A method and method of mastering a serial bus. A serial bus is monitored in order to detect a quiescent period on the bus. Responsive to a detection of a quiescent period, bus signals to a first master device of the serial bus are interrupted, isolating the first bus master from the rest of the bus. Once the first bus master is isolated, a second bus master may operate on the bus, free from potential deleterious interference from the first bus master. When the second bus master is finished operating, it may cause the re-coupling of the bus, restoring the capability of the first bus master to operate.

Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing

Abstract: A method and system transfer read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations of the memory device. The method includes placing a sequence of read data words on the data bus and applying a data bus inversion signal on the data masking pin, the data bus inversion signal indicating whether the data contained each read data word has been inverted. Another method and system transfer data over a data bus. The method includes generating a sequence of data words, at least one data word including data bus inversion data. The sequence of data words is applied on the data bus and is thereafter stored. The data bus inversion data is applied to invert or not invert the data contained in the stored data words.

Bus function authentication method, apparatus and computer program

Abstract: Devices connected to a communications bus are selectively accessed to the bus that communicates between one or more devices and a host machine. On the basis of analyzed device characteristics, communication between the device and the host machine via the bus is enabled or disabled. Filtering software intercepts the results of a GET_DESCRIPTOR function and compares same with the contents of a disallowed device characteristic list. If the device is disallowed, data flow is remapped to a generic driver which halts configuration or communication on the bus. Alternatively, configuration/communication on the bus is halted for that device.

Method and system to implement a system event log for system manageability

Abstract: Embodiments of the present invention provide a system event log for a computer system. The system event log may comprise a RAM coupled to a system bus. The system event log may be configured to record information in the RAM corresponding to bus transactions on the system bus. The information may be used to de-bug system problems.