Showing papers on "System bus published in 2020"

An Adaptive Approach for Effective Power Management in DC Microgrid Based on Virtual Generation in Distributed Energy Sources

Abstract: This paper proposes a new control algorithm for effective power management in the dc microgrid with renewable energy sources (RES) and energy storage system (ESS). This scheme overcomes the average power sharing and bus voltage regulation problems with maximum utilization of source power. In the source, the additional power available beyond its average rated value is treated as virtual generation. The new references are generated considering virtual generation. The novelty of the proposed algorithm is to bring the virtual generation effectively in operation. The virtual generation of the individual source is based on available power source. The proposed algorithm reduces the charging/discharging cycles of ESS and, hence, enhances the life span of ESS. It reduces the stress on interfaced converters, regulates the system bus voltage, reduces power fluctuations on the sources, and enhances stability. The proposed control algorithm is verified in MATLAB simulation and in real-time simulator.

A Fuzzy Logic Based Supervisory Control for Power Management in Multibus DC Microgrid

Abstract: The dc microgrid consists of renewable energy sources, energy storage system, and loads. The power output of these RESs is intermittent in nature. This raises the problem of power sharing among the sources and bus voltage regulation. This article proposes a new fuzzy logic based control scheme to mitigate power sharing mismatch during the variation in available power of RESs. It exploits the nonlinear mapping between sources power sharing with variation in available power. The novel fuzzy logic controller improves the system bus voltage regulation under different operating conditions. It is simple in design and does not need knowledge about a complex mathematical model of the overall system. The experimental results are presented which shows the superiority of the proposed control under different operating conditions over the conventional control.

22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme

Abstract: Rapidly evolving artificial intelligence (Al) technology, such as deep learning, has been successfully deployed in various applications: such as image recognition, health care, and autonomous driving. Such rapid evolution and successful deployment of Al technology have been possible owing to the emergence of accelerators, such as GPUs and TPUs, that have a higher data throughput. This, in turn, requires an enhanced memory system with large capacity and high bandwidth [1]; HBM has been the most preferred high-bandwidth memory technology due to its high-speed and low-power characteristics, and 1024 IOs facilitated by 2.5D silicon interposer technology, as well as large capacity realized by through-silicon via (TSV) stack technology [2]. Previous-generation HBM2 supports 8GB capacity with a stack of 8 DRAM dies (i.e., 8-high stack) and 341GB/s (2.7Gb/s/pin) bandwidth [3]. The HBM industry trend has been a speed improvement of 15~20% every year, while capacity increases by 1.5-2x every two years. In this paper, we present a 16GB HBM2E with circuit and design techniques to increase its bandwidth up to 640GB/s (5Gb/s/pin), while providing stable bit-cell operation in the 2nd generation of a 10nm DRAM process: featuring (1) a data-bus window-extension technique to cope with reduced $t_{cco}$ , (2) a power delivery network (PDN) designed for stable operation at a high speed, (3) a synergetic on-die ECC scheme to reliably provide large capacity, and (4) an MBIST solution to efficiently test large capacity memory at a high speed.

A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing

Abstract: We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two identical chiplets is implemented in 7-nm CMOS with 15 metal layers and has four Arm Cortex-A72 processor cores operating at 4.0 GHz. A bidirectional mesh bus with 2-mm flop-to-flop distance is distributed throughout the chiplet for high-speed on-die data transport above 4.0 GHz. The chiplets communicate with each other through ultrashort reach (0.5 mm long) interposer channels using a Low-voltage-In-Package-INterCONnect (LIPINCON) clock-forwarded parallel interface. The scalable link module offers 320 GB/s of aggregate bandwidth, operating at 8.0 Gb/s/pin and 0.3-V transmitter swing without receiver termination to achieve 0.56-pJ/bit energy efficiency and 1.6-Tb/s/mm2 bandwidth density. Measurements of the fabricated SiP validate the functionality and performance of the cores, on-die data bus, and inter-chiplet link. The built-in LIPINCON eye-scan feature validates inter-chiplet connectivity at 8.0 Gb/s with an eye opening of 244 mV and 0.69 UI.

RDON: a rack-scale disaggregated data center network based on a distributed fast optical switch

Abstract: Aiming to solve the low utilization and high operational cost in current data centers and the diversified resource requirements for different application types, we propose and investigate what we believe to be a novel rack-scale disaggregated optical data center network (RDON). Different types of hardware resources (i.e., CPU, memory, and storage) are deployed in standalone resource pools of the RDON. The RDON architecture encompasses nanosecond distributed fast optical switches for the low latency and high bandwidth interconnects between the computing and memory nodes, while electrical packet switches are utilized to support the traffic of latency insensitivity and low bandwidth between memory nodes and storage nodes. By replacing the onboard data bus with a network interconnection, RDON architecture can provide a fine granularity hardware resource and relieve the constraints of server-centric architecture. To assess the performance of the RDON under realistic scenarios, statistics of diverse applications are captured from the data center lab. The RDON is modeled based on the OMNeT++ discrete event simulator and compared with the server-centric architecture. Numerical results show that the performance of the RDON is closely coupled with the type of deployed application. Compared to the server-centric architecture, the RDON can achieve up to ${2.44\times}$2.44× faster running time when running a single application, whereas at most ${2.25\times}$2.25× is the fastest running time under coexisting diverse types of applications. Finally, the analysis of costs and power consumption show that, with respect to server-centric architecture, the RDON requires 21.5% extra capital cost but 46.7% less power consumption.

FLS-Based Collision Avoidance Cyber Physical System for Warehouse Robots using FPGA

Abstract: The overperforming enormous number of Automated Guided Vehicles (AGV) that have been adopted in warehouses recently proved their capabilities of speeding up the parcel exchange process in comparing with human capabilities. In order to increase the overall performance of these AGVs, we introduced an Artificial Intelligence (AI) based processing unit for the purpose of enhancing the collaborative diagnostics and decision making in such applications by exchanging feedback data frames to the center hub. The proposed AI-based controller is based on a multi-core Fuzzy Logic System (FLS) is to differentiate the level of collision probability in a Cyber Physical System (CPS) using asymmetric data bus width architecture. The proposed systolic FLS architecture in this paper has been designed using VHDL to be interfaced with a three TFmini Plus Lidar Sensors and three MaxSonar ultrasonic sensors using the Intel Altera OpenVINO FPGA board. The proposed systolic FLS processing unit achieved a processing computational speed of about 14.36 GOPS at maximum operating frequency of 270.86 MHz while consuming about 58.56 mW as a core dynamic thermal power dissipation and around 28.38 mW as a 1/0 thermal power dissipation.

Computational SRAM design automation using pushed-rule bitcells for energy-efficient vector processing

Abstract: This paper presents a new methodology for automating the Computational SRAM (C-SRAM) design based on off-the-shelf memory compilers and a configurable RTL IP The main goal is to drastically reduce the development effort compared to a full-custom design, while offering a flexibility of use and a high-yield production The proposed C-SRAM architecture has been developed to process energy-efficient vector data coupled with a scalar processor, while limiting the data transfer on the system bus The results obtained by post P&R simulations show that 2RW and 4RW C-SRAM configurations using the double pumping technique achieved the highest performance to process vectorized MAC operations compared to the others configurations Moreover, it has been shown that the impact of the digital wrapper decoding and executing the instructions can be mitigated by increasing the memory cut size to represent less than 10% in area and 20% in power consumption

Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators

Abstract: Convolutional Neural Network (CNN) accelerators have gained popularity due to their ability to speed up the CNN based applications. However, the energy efficiency of these accelerators is limiting their ubiquitous usage in energy-constrained devices. A significant fraction of their energy consumption results from off-chip memory accesses. In order to get high throughput, these accelerators connect to off-chip memory by a wide data bus. However, accessing the data of size, not a multiple of the bus width, results in wastage of energy. We observed that off-chip memory accesses could be reduced significantly by partitioning the data that optimally utilizes bus width and increases the number of aligned accesses. In this work, we propose a bus width aware approach to determine the optimal partition of the convolution layers to reduce the off-chip memory accesses. Our tool evaluates the off-chip memory accesses for different data partitions, and data reuse schemes to find the optimal partition. We have experimented with two popular CNNs, VGG16 and AlexNet. Our approach reduces off-chip memory accesses of VGG16 by 16% and 29% and of AlexNet by 9% and 16% on 64 and 128 bits data bus, respectively, compared to the state of the art approach.

Integration of ZigBee based GPS receiver to CAN network for precision farming applications

Abstract: Precision farming applications are often data centric and aim collecting data from a set of sensor modules to be delivered to the central computer. For this aim, the ISO 11783 protocol which uses the Controller Area Network (CAN) as a data link protocol to perform the data communication are used to standardize and provide the serial data communication as wired between the various sensor modules and the central computer a plug/play approach. Many different types of sensors may use to collect temporal and spatial variability in precision farming applications. Especially GPS receivers are the most important sensor in a precision farming application. And also, different data bus protocols can be used for collected data transmission to the central computer. In this context, wireless sensor protocols, especially ZigBee, is gaining popularity for managing precision farming through real-time monitoring of agricultural variability. Various parameters in the precision farming can be monitored and controlled using ZigBee communication integrated with the CAN bus. In this paper, integration of the wired CAN Bus and ZigBee communication was designed, developed and implemented. In this system, the data regarding the geographical coordinate is extracted from the GPS receiver with the help of the ZigBee communication and send it to a central computer with the help of wired CAN Bus. This method has been implemented in order to adapt the ZigBee messages to the CAN Bus and reduce wire using. Finally, the data flow within designed system between CAN and ZigBee data frames was described. In this study, multiple CAN frames usage and handshaking mechanism are explained for sending sensor data longer than 64 bits. This system’s advantage is not only reduce cabling cost and increase the communication speed but also provide dynamic, flexible and applicable communication in precision farming applications.

System on chip

Abstract: The invention provides a system on chip The system on chip comprises a field programmable gate array; the field programmable gate array comprises a micro-control unit kernel circuit, a system bus, aninterrupt control circuit, an instruction memory, a data memory and external equipment, wherein the system bus, the interrupt control circuit, the instruction memory and the data memory are respectively connected with the micro-control unit kernel circuit, and the system bus is also connected with the interrupt control circuit and external equipment; the micro-control unit kernel circuit is basedon an RISC-V instruction set architecture, and is used for reading an instruction from the instruction memory, decoding the instruction, processing the instruction and corresponding data according toa decoding result, and managing, responding and processing interruption in real time through the interruption control circuit According to the system-on-chip, the expansibility, portability and usability of the whole system are improved, and the design difficulty of designers is reduced

Hardware Fingerprinting for the ARINC 429 Avionic Bus

Abstract: ARINC 429 is the most common data bus in use today in civil avionics. Despite this, the protocol lacks any form of source authentication. A technician with physical access to the bus is able to replace a transmitter by a rogue device, and receivers will accept its malicious data as they have no method of verifying the authenticity of messages.

Three-Phase Distribution System Load Flow Analysis Using Sequence Components

Abstract: Electric power distribution system are usually unbalance. Therefore, a power flow method that can handle the three-phase configuration of the power system is needed so that the system planning and operation can properly be carried out. In the case of three-phase distribution system power flow analysis, for each system bus (except for substation bus), the voltage magnitude and angle of the three phases must be calculated. These calculations are carried out under certain loading conditions. After these voltages have been calculated, the electric power flows and losses in the distribution lines, and the substation power can also be determined. This paper proposes a new technique for three-phase distribution system power flow analysis using sequence components. The new formulation for the power flow problem in terms of sequence components is also proposed and developed in this paper. The application of sequence components has the advantage that the size of the problem can effectively be reduced, and solution to the power flow problem will be easier to find. Case study using a representative distribution test system confirms the validity of the proposed method where comparative studies between the proposed (i.e. sequence components based) method and the phase components based method are carried out.

Deterministic cache-based execution of on-line self-test routines in multi-core automotive system-on-chips

Abstract: Traditionally, the usage of caches and deterministic execution of on-line self-test procedures have been considered two mutually exclusive concepts At the same time, software executed in a multi-core context suffers of a limited timing predictability due to the higher system bus contention When dealing with selftest procedures, this higher contention might lead to a fluctuating fault coverage or even the failure of some test programs This paper presents a cache-based strategy for achieving both deterministic behaviour and stable fault coverage from the execution of self-test procedures in multi-core systems The proposed strategy is applied to two representative modules negatively affected by a multi-core execution: synchronous imprecise interrupts logic and pipeline hazard detection unit The experiments illustrate that it is possible to achieve a stable execution while also improving the state-of-the-art approaches for the on-line testing of embedded microprocessors The effectiveness of the methodology was assessed on all the three cores of a multi-core industrial System- on-Chip intended for automotive ASIL D applications

Hardware Fingerprinting for the ARINC 429 Avionic Bus

Abstract: ARINC 429 is the most common data bus in use today in civil avionics. However, the protocol lacks any form of source authentication. A technician with physical access to the bus is able to replace a transmitter by a rogue device, and the receivers will accept its malicious data as they have no method of verifying the authenticity of messages. Updating the protocol would close off security loopholes in new aircraft but would require thousands of airplanes to be modified. For the interim, until the protocol is replaced, we propose the first intrusion detection system that utilizes a hardware fingerprinting approach for sender identification for the ARINC 429 data bus. Our approach relies on the observation that changes in hardware, such as replacing a transmitter or a receiver with a rogue one, modify the electric signal of the transmission. Because we rely on the analog properties, and not on the digital content of the transmissions, we are able to detect a hardware switch as soon as it occurs, even if the data that is being transmitted is completely normal. Thus, we are able to preempt the attack before any damage is caused. In this paper we describe the design of our intrusion detection system and evaluate its performance against different adversary models. Our analysis includes both a theoretical Markov-chain model and an extensive empirical evaluation. For this purpose, we collected a data corpus of ARINC 429 data traces, which may be of independent interest since, to the best of our knowledge, no public corpus is available. We find that our intrusion detection system is quite realistic: e.g., it achieves near-zero false alarms per second, while detecting a rogue transmitter in under 50ms, and detecting a rogue receiver in under 3 seconds. In other words, technician attacks can be reliably detected during the pre-flight checks, well before the aircraft takes off.

I2C bus expansion interface, control method thereof and system on chip

Abstract: The invention discloses an I2C bus expansion interface, a control method thereof and a system on chip. The I2C bus expansion interface is characterized in that the I2C bus expansion interface is realized on the basis of logic resources of an FPGA (Field Programmable Gate Array) and is used for connecting a processor and external equipment, and the I2C bus expansion interface comprises a pluralityof I2C peripherals which are respectively connected with the corresponding external equipment; a system bus interfaces connected with the system bus of the processor and used for establishing communication connection with the processor; and a controller connected with the system bus interface and the plurality of I2C peripherals and used for operating the corresponding I2C peripherals accordingto the peripheral address signals received by the system bus interface from the processor so as to further realize I2C communication with the corresponding external equipment. By means of a mode, thenumber and functions of the I2C bus interfaces can be dynamically controlled by means of the programmable characteristic of the FPGA, and expansibility and usability of the processor are improved.

Routing rule obtaining method, device, and system

Abstract: A routing rule obtaining method, device, and system are provided. The method is applied to an MEC system and performed by a data bus controller, including: obtaining service information of at least one service in the MEC system, where service information of each service includes a service type and a service identity; generating a routing rule according to the service information of the at least one service, where the routing rule is used to indicate at least one path through which a data packet can pass; and sending the routing rule to a data bus, so that the data bus forwards, according to the routing rule, a received data packet to a service corresponding to the data packet. The service information of each service is dynamically obtained, so as to update a path indicated in a routing rule.

High-power fiber laser modular heat management device capable of realizing spatiotemporal modulation of temperature distribution

Abstract: The invention provides a high-power fiber laser modular heat management device capable of realizing spatiotemporal modulation of temperature distribution. The high-power optical fiber laser modular heat management device comprises a modular water cooling disc (1), a control module (2), a control bus (3), a data bus (4) and a temperature rapid regulation and control module (5). The modular water cooling disc (1) comprises a plurality of optical fiber temperature adjusting pieces (11) for adjusting the temperature of high-power laser optical fibers fixed thereto to be within a specified norm value or range. The number of the temperature rapid regulation and control modules (5) is the same as that of the optical fiber temperature adjusting pieces (11), and the temperature rapid regulation andcontrol modules are in one-to-one correspondence connection with the optical fiber temperature adjusting pieces (11). The control module (2) is connected with the plurality of temperature rapid regulation and control modules (5) through the control bus (3); and the control module (2) is connected with the optical fiber temperature adjusting pieces (11) through the data bus (4) and is used for acquiring temperature data of the optical fiber temperature adjusting piece (11) so as to form an adjusting and controlling instruction for controlling the temperature rapid regulation and control modules (5).

Dynamic page state aware scheduling of read/write burst transactions

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.

Adaptive headlamp system for vehicles

Abstract: A vehicle headlamp system includes a vehicle supported power and control system including a data bus. A sensor module can be connected to the data bus to provide information related to environmental conditions or information relating to presence and position of other vehicles and pedestrians. A separate headlamp controller can be connected to the vehicle supported power and control system and the sensor module through the bus. The headlamp controller can include an image frame buffer that can refresh held images at greater than 30 Hz speed. An active LED pixel array can be connected to the headlamp controller to project light according to a pattern and intensity defined by the image held in the image frame buffer and a standby image buffer can be connected to the image frame buffer to hold a default image.

DDR memory bus with a reduced data strobe signal preamble timespan

Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

FPGA-based universal asynchronous transceiving transmitter and system-on-chip

Abstract: The invention discloses an FPGA (Field Programmable Gate Array)-based universal asynchronous transceiving transmitter and an on-chip system. The universal asynchronous transceiving transmitter is realized based on FPGA logic resources, is connected with a micro-control unit and external equipment, and comprises a system bus interface, a system bus connected with the micro-control unit and used forestablishing communication connection with the micro-control unit; the plurality of peripheral UARTs are respectively connected with the corresponding external devices and are used for establishing communication connection with the corresponding external devices; and the controller is connected with the system bus interface and the plurality of peripheral UARTs and is used for controlling the corresponding peripheral UARTs according to the addresses received by the system bus interface from the micro-control unit. By means of the mode, dynamic adjustment and management of the UART by the MCUare achieved, expansibility and universality of the MCU are improved, and design complexity is reduced.

Methods and apparatus for high-speed data bus connection and fabric management

Abstract: Methods and apparatus for efficient scaling of fabric architectures such as those based on PCIe technology, including up to very large fabrics and numbers of hosts/devices for use in ultra-high performance applications such as for example data centers and computing clusters. In one aspect, methods and apparatus for using Non- Transparent Bridge (NTB) technology to export Message Signaled Interrupts (MSIs) to external hosts are described. In a further aspect, an 10 Virtual Address (10 V A) space is created is used as a method of sharing an address space between hosts, including across the foregoing NTB(s). Additionally, a Fabric Manager (FM) entity is disclosed and utilized for programming e.g., PCIe switch hardware to effect a desired host/fabric configuration.

Vehicle information management

Abstract: According to an example embodiment, a method for transferring vehicle information in a vehicle information system (100) of a motor vehicle (104)is provided, wherein entities of the vehicle information system (100) are connected to each other by a data bus (170). The method comprises processing the vehicle information through a sequence of one or more processing components (801,803,805,807,901,903,905) arranged in a signal path between the data bus (170) and a digital instrument panel provided via a user interface in the motor vehicle (104), said processing comprising, in each processing component (801,803,805,807,901,903,905), receiving input data from direction of an input to the signal path, carrying out a respective predefined processing operation for generating output data on basis of the input data, and providing the output data towards an output of the signal path; and transferring status data through said sequence of processing components (801,803,805,807,901,903,905) from direction of the data bus (170) towards the digital instrument panel, said transferring comprising, in each processing component (801,803,805,807,901,903,905), receiving input status data from direction of the data bus (170), and conveying the input status data in an output status data towards the digital instrument panel.

System-on-chip and memory

Abstract: The invention discloses a system-on-chip and a memory. The system-on-chip comprises a processor and a memory, the memory is connected with a system bus of the processor, the memory is realized based on logic resources of an FPGA. The memory comprises: a system bus interface which is connected with the system bus and is used for establishing communication connection with the processor; a pluralityof functional interface modules which are used for storing data and instructions; and a controller which is connected with the system bus interface and the plurality of functional interface modules and is used for carrying out read operation or write operation on the corresponding functional interface modules according to the storage address signals received by the system bus interface from the processor. Through the mode, the programmable characteristic of the FPGA is utilized, the capacity of the memory can be dynamically allocated, the usability of the FPGA is improved, and the design difficulty of the memory is reduced.

Online Bus Impedance Estimation and Stabilization of DC Power Distribution Systems: A Method Based on Source Converter Loop-Gain Measurement

Abstract: In this work a method of stability monitoring and adaptive stabilization is proposed for DC power distribution systems (PDS) It has been shown that the stability of DC PDS can be effectively analyzed using the system bus impedance, which is calculated as the parallel combination of all individual impedances of the converters connected to the DC bus Conventionally, these impedances are measured in several lengthy measurements This work, instead, proposes a method for online estimation of the bus impedance using the voltage loop-gain of the source converter and the input impedance of the load converter In this approach, all the needed information for system stability monitoring and adaptive stabilization are obtained in a single measurement by injecting a wide-band perturbation in the source converter control platform This method has several advantages, namely the simplification of online stability monitoring and stabilization as well as elimination of the need for any communications among converters The proposed method is validated by simulation and experimental results

Comprehensive train control system capable of adapting to foreign requirements

Abstract: The invention provides a comprehensive train control system capable of adapting to foreign requirements. The comprehensive train control system includes vehicle-mounted equipment and ground equipment.The vehicle-mounted equipment integrates a CTCS-3 vehicle-mounted train control system unit and a foreign vehicle-mounted train control system unit, the CTCS-3 vehicle-mounted train control system unit and the foreign vehicle-mounted train control system unit are connected through a relay form, and switching between the CTCS-3 vehicle-mounted train control system unit and the foreign vehicle-mounted train control system unit is carried out in an inter-stage switching manner. The ground equipment includes a station system, a dispatching station system, a CTC center system, an RBC center systemand a GSM-R core network system, the station system and the dispatching station system are in data connection with the CTC center system, the RBC center system and the GSM-R core network system through a data bus. The system can meet some general operating requirements of mainstream markets at home and abroad and achieves compatibility with existing train control systems in target countries at the present stage.

Motion Object Tracking System Based on FPGA

Abstract: The technology of moving object detection and tracking has been widely used in consumer electronics, industrial detection, security monitoring and intelligent transportation. This paper uses FPGA(Field Programmable Gate Array) as the platform, because its unique parallel processing mechanism and powerful computing ability can improve the processing speed and performance of the system. At the same time, a design and implementation of SOPC (system on programmable chip) system based on NIOSII is proposed. The system bus clock reaches 266.67MHz. Combined with simple and effective detection and tracking algorithm, the processing speed of motion tracking is greatly improved by using floating-point hardware acceleration. The system can process 320 * 240 true color images at a speed of 20 frames per second. The tracking accuracy is over 93%. The results show that the system has achieved the expected function, has good real-time performance and tracking accuracy, and has good portability, and has a wide application prospect.

Block-wise matrix multiplication system

Abstract: The disclosure relates to a processor including an N-bit data bus configured to access a memory; a central processing unit CPU connected to the data bus; a coprocessor coupled to the CPU, including a register file with N-bit registers; an instruction processing unit in the CPU, configured to, in response to a load-scatter machine instruction received by the CPU, read accessing a memory address and delegating to the coprocessor the processing of the corresponding N-bit word presented on the data bus; and a register control unit in the coprocessor, configured by the CPU in response to the load-scatter instruction, to divide the word presented on the data bus into K segments and writing the K segments at the same position in K respective registers, the position and the registers being designated by the load-scatter instruction.