Showing papers on "Transistor published in 1974"

A new ferroelectric memory device, metal-ferroelectric-semiconductor transistor

Abstract: The ferroelectric field effect has successfully been demonstrated on a bulk semiconductor (silicon) using a thin ferroelectric film of bismuth titanate (Bi 4 Ti 3 O 12 ) deposited onto it by RF sputtering. A new memory device, the metal-ferroelectric-semiconductor transistor (MFST); has been fabricated. This device utilizes the remanent polarization of a ferroeletric thin film to control the surface conductivity of a bulk semiconductor substrate and perform a memory function. The capacitance-voltage characteristics of the metal-ferroelectric-semiconductor structure were employed to study the memory behavior. The details of the study together with a preliminary results on the MFST are presented.

High-speed integrated logic with GaAs MESFET's

Abstract: The feasibility of using GaAs metal-semiconductor field-effect transistors (GaAs MESFET's) in fast switching and high-speed digital integrated circuit applications is demonstrated. GaAs MESFET's with 1-/spl mu/m gate length are shown to have a current-gain-bandwidth product f/SUB T/ equal to 15 GHz. These devices exhibit a 15 ps internal delay in a large-signal switching test. A simple logic circuit consisting of MESFET's and Schottky diodes was monolithically integrated on a semiinsulating GaAs substrate. This logic circuit exhibits a propagation delay of 60 ps with no output load, and 105 ps when its output is loaded by three similar logic gates. A useful bandwidth of approximately 3 GHz is observed.

Current multiplication in metal-insulator-semiconductor (MIS) tunnel diodes☆

Abstract: In contrast to thick insulator structures, metal-insulator-semiconductor (MIS) diodes with very thin insulating layers (< 30 A for the silicon-silicon dioxide system) allow appreciable tunnel current flow between the metal and the semiconductor causing the semiconductor to depart significantly from thermal equilibrium conditions when the diode is biased. Under such conditions, recent experiments have demonstrated that multiplication of minority carrier current can occur in the contact region. This multiplication process is described in detail by deriving analytical expressions characterizing this process and its dependence upon the metal, insulator, and semiconductor parameters for one specific class of diode. Numerical methods are used to investigate the multiplication properties under more general conditions. Solutions obtained by this method indicate that values of the small signal multiplication factor, M, in the range of 102–103 can be obtained with appropriately designed diodes. The applications of the multiplication process to a transistor structure and to a photodiode with internal multiplication properties are described briefly.

The injection model-a structure-oriented model for merged transistor logic (MTL)

Abstract: The merged transistor device is represented by assigning separate diodes to the various electron and hole injections along the active p-n junction. Where collection takes place, current sources are introduced. Measurement procedures are described that allow a quantitative separation of the various injections, and hence the determination of the model parameters. Results of such measurements are given. Device terminal parameters, like current gains and storage time constants, can be predicted from the measurements for devices of arbitrary horizontal geometry, so that the injection model can serve as a device optimization tool. As a circuit analysis model it allows representation of the internal device series resistances which would not be possible with an Ebers-Moll model. The injection model is significant beyond the merged transistor logic (MTL) aspects as it renders a better insight into bipolar devices, particularly into lateral p-n-p and saturated n-p-n transistors.

Insulated-gate thin film transistor with low leakage current

Abstract: An insulated-gate thin film transistor is provided with low leakage drain current. A second semiconductor layer makes contact with the source electrode and the semiconductor layer forming the channel of the transistor at least between the source and drain electrodes. The second semiconductor layer is of opposite type conductivity from the channel semiconductor layer and preferably forms a PN heterojunction with the channel semiconductor layer. Alternatively, a metal layer may be used in place of the second semiconductor to form a Schottky-barrier junction with the channel semiconductor layer instead of a PN junction. Preferably, the channel semiconductor layer and the second semiconductor layer or the metal layer are sequentially evaporation deposited through the same deposition mask onto a substrate from evaporant sources spaced substantially different distances from the substrate so that the sequential layers are deposited on first and second overlapping areas of the substrate.

The GaAs inversion-type MIS transistors

Abstract: The alloying technique for source and drain n + regions and the chemical-vapor-deposited double layer films of Al 2 O 3 and SiO 2 were found to be useful for the realization of the inversion channel GaAs MIS transistors. This is because the alloying was carried out at much lower temperature than donor diffusion and the stability was remarkably improved by using the double layer above mentioned. The transistor had an effective mobility of 2240 cm 2 /V.sec, and the threshold voltage was controlled by changing the thickness ratio of the two films. The characteristics of the transistor were compared with the theoretical curves which were calculated by considering several limiting factors; bulk charges, a saturation velocity of carriers and series resistances. The fairly good agreement between the two was found. Some discrepancies, recognized in some cases, seemed to be attributable to some unknown parameters in the theory and to influences of interface states.

Electronic Circuits and Applications

Abstract: Partial table of contents: LEARNING THE LANGUAGE. Fundamental Concepts. Linear Resistive Networks. Dependent Sources. Operational Amplifiers. Capacitance and Inductance. ELECTRONIC DEVICES. Electrical Conduction Processes. Diode Circuits and Applications. Physical Electronics of Transistors. Large-Signal Transistor Circuits. Small-Signal Models and Circuits. LINEAR CIRCUITS AND SYSTEMS. Linear System Response. Frequency Response in Linear Systems. Signal-Processing in Linear Systems. APPLICATIONS.

Design and operation of a floating gate amplifier

Abstract: A unique amplifier configuration is examined that fully exploits the intrinsically high signal-to-noise performance of charge-coupled devices (CCD's). In this amplifier, the signal charge is detected with a conducting `floating gate' embedded in the oxide between a bias electrode and the silicon substrate. The change of voltage on the floating gate produced by the signal charge in the CCD channel is then used to modulate the current flow in a metal-oxide-semiconductor (MOS) transistor. The signal charge remains isolated and can be moved downstream in the CCD channel; thus, it can be detected again by other similar structures. Computer analysis, test structure design, and experimental results of a floating gate amplifier (FGA) are presented.

Level shifter circuit

Abstract: An improved TTL to MOS voltage level shifter circuit utilizes a totem pole output stage consisting of a pull-up junction transistor and a pull-down saturation junction transistor, an intermediate stage consisting essentially of a saturation junction transistor, an input stage consisting essentially of a diode and a saturation junction transistor, and current spike inhibit circuitry which consists essentially of a saturation junction transistor connected between the input stage and the base of the pull-down transistor. The current spike inhibit transistor, which turns on with the pull-down transistor, has a greater turnoff time than the pull-down transistor and consequently provides a relativley low impedance discharge path connected to the base of the pull-down transistor which allows the pull-down transistor to turn off before the pull-up transistor turns on. This helps insure against output current spikes that occur if the pull-up and pull-down transistors conduct simultaneously.

Design and Performance of Microwave Amplifiers with GaAs Schottky-Gate Field-Effect Transistors

Abstract: The design and performance of an X-band amplifier with GaAs Schottky-gate field-effect transistors are described. The amplifier achieves 20 /spl plusmn/ 1.3-dB gain with a 5.5-dB typical noise figure (6.9 dB maximum) over the frequency range of 8.0-12.0 GHz. The VSWR at the input and output ports does not exceed 2.5:1. The minimum output power for 1-dB gain compression is +13 dBm, and the intercept point for third-order intermodulation products is +26 dBm. The design of practical wide-band coupling networks is discussed. These networks minimize the overall amplifier noise figure and maintain a constant gain in the band.

Terminal-oriented model for merged transistor logic (MTL)

Abstract: A simple device model is derived to represent merged transistor logic (MTL) circuit behavior. Using the Ebers-Moll equations, the proper definitions of the various current gains are derived, and it is shown that MTL devices can be basically interpreted as n-p-n transistors having an additional base current source. The relations between the intensity of this source and the current actually supplied are derived. Time behavior is modeled according to the charge control concept. Using this model, circuit delays are given as a function of current gains, collector and emitter time constants, supply current, and of fan-out.

Fully ion-implanted bipolar transistors

Abstract: Technology for the fabrication of fully ion-implanted bipolar transistors with arsenic emitters and boron bases is described. This technology results in extremely uniform distributions of electrical parameters, e.g,, h FE = 113 with a standard deviation of 1.3 across a wafer. In addition, it can produce a wide range of doping profiles and hence, a wide range of device performance. Using very similar processing schedules, transistors with h FE from 20 to >5000 and with f T 's from 1.5 to 8.1 GHz have been made. The features of implanted arsenic which make it an excellent emitter are: 1) it can be implanted to high doses with only a small deep side tail which has a negligible effect on the typical transistor base; 2) because of the concentration dependence of its diffusion constant, it forms a very abrupt profile after diffusion; and 3) when diffused a short distance (∼1000 A) away from the implanted region, high-lifetime material can be incorporated into the emitter and hence, high-gain low-leakage transistors can be made. When the arsenic emitter is combined with a double-peaked boron-implanted base, precise independent control of the active and inactive base properties of the device can be achieved. This independence allows considerable latitude in the choice of device parameters for fully implanted bipolar transistors.

Contactless test method for integrated circuits

Abstract: A method is provided for contactless testing of an integrated circuit by fabricating, integrally with the integrated circuit, semiconductor switch elements, that is, thyristors, transistors and combinations thereof, that are connected to power and/or signal electrical inputs of the integrated circuit. Base regions of the switch elements are selectively exposed to a fine-dimensioned electron beam to switch the elements and supply desired electrical inputs at the connected inputs of the integrated circuit. The integrated circuit can thus be selectively tested preferably by segments and modules. After testing, the switch elements are disconnected from the integrated circuit, and the integrated circuit selectively connected preferably while accommodating and passivating defective components and modules of the circuit.

Protection circuit for insulated-gate field-effect transistors

Abstract: Two current-carrying paths are connected in parallel between a signal input terminal and an internal node to which are connected the gate electrodes of insulated-gate field-effect transistors to be protected. One path includes the conduction path of a first transistor of one conductivity type connected in series with a first diode poled in a direction to charge the internal node and the other path includes the conduction path of a second transistor of second conductivity type in series with a second diode poled in a direction to discharge the internal node. The control electrodes of the first and second transistors are connected to points of operating potential rendering the first transistor conductive in the source follower mode for input signals of one polarity and rendering the second transistor conductive in the source follower mode for input signals of opposite polarity.

Switching circuit having floating gate mis load transistors

Abstract: A switching circuit comprises a driving MIS field-effect transistor, and a load MIS field-effect transistor, the gate of which is electrically floating and is so charged as to produce a gate voltage greater than the supply voltage of the load MIS field-effect transistor

Threshold voltage controllability in double-diffused-MOS transistors

Abstract: The sensitivity of double-diffused metal-oxide-semiconductor (D-MOS) transistor threshold voltage to fabrication process variations has been studied. Computed impurity profiles are used to study the process dependencies. For the double diffused process, the channel predeposition is shown to be the most critical step in threshold voltage control for long channel devices. Experimental results confirm this relationship. Process considerations appropriate for the fabrication of short channel D-MOS devices are also presented. Computed variations of threshold voltage with expected process tolerances for the channel predeposition are consistent with experimental results. Computer results show that for D-MOS deviceswith source junction depths of about 1 µm and channel lengths greater than 2 µm, threshold voltage can be controlled to ±20 percent using thermal diffusion and ±5 percent using ion implanted predeposition. Greater variation in threshold voltage is found for shorter channel lengths.

Comparison of one- and two-dimensional models of transistor thermal instability

Abstract: The I C -V CE locus predicted by a one-dimensional model of thermal instability is compared with the I C -V CE locus predicted by a numerical model which accounts for nonuniform heat generation over the transistor area and also two-dimensional heat flow within the heat sink. Both models include the effects of distributed emitter and base ballast resistance, as well as the magnitude and temperature dependence of current gain. An important result obtained from this comparison is that the I-V loci predicted by the two models are very nearly the same, even though the temperature and power density profiles over the transistor die are distinctly different. It is the I-V locus which is of most practical interest, since it is one portion of the boundary of the forward safe operating area (SOA). The similarity of the I-V loci should allow one to use the simple one-dimensional model to predict a particular SOA, even though the assumptions under which the model was originally derived are not valid at the onset of thermal instability. Confirmation of this approach has been obtained by demonstrating good agreement between the measured safe operating area and that predicted by the one-dimensional model for both single- and double-diffused transistors. The predicted improvement due to the addition of discrete emitter resistors has also been verified by SOA measurements on actual devices. The device parameters which are important in determining SOA are the effective emitter and base resistances, the magnitude and temperature dependence of current gain, and the effective thermal resistance between the active region of the transistor and its heat sink. The quantitative dependence of SOA due to each of these parameters is described.

VMOS—A new MOS integrated circuit technology

Abstract: A new V-groove MOS integrated circuit technology (VMOS) is described It makes use of preferential etching of silicon to define the channels of the MOS transistors The fabrication involves either a three or four mask process and is capable of producing either silicon gate or standard metal gate transistors The technology results in very short channel length devices using non-critical alignment tolerances Despite the short channel length, the VMOS transistor exhibits lower output conductance and higher breakdown voltage than a standard MOS transistor A first order theory is presented for the VMOS transistor along with measurements made on test devices of various channel lengths Some integrated circuit applications of the technology are also presented, including an R-S fiip-flop and a 27-stage bucket brigade shift register The advantages of the VMOS technology in such applications are discussed

Logic level translator

Abstract: A logic level translator utilizes a TTL logic gate, a current switch, and a clamp circuit to convert CML level binary signals into TTL level binary signals. The translator provides isolation between the TTL ground and the CML ground in order to reduce noise in the CML portion of the circuit. The clamp circuit prevents a switching transistor in the current switch from reaching saturation, thereby increasing the speed of operation of the translator. A portion of the current switch provides a quick pulldown of a switching transistor in the TTL circuit to reduce noise in the TTL circuit.

Method of fabricating injection logic integrated circuits using oxide isolation

Abstract: An integrated injection logic circuit cell structure and its fabrication are simplified. A pattern of oxide isolation regions is used to define, at least partially, the introduction of two types of impurities in such a way as to reduce the number of masking steps. Certain of these oxide regions do not penetrate through the conventional epitaxial layer, leaving a lateral buried path to serve as the base of a lateral injection transistor. A pattern of polycrystalline silicon containing impurities is used both as a diffusion source and an interconnection.

SCR memory cell

Abstract: SCR MEMORY CELL Abstract A bistable memory cell (stores one binary digit or bit) suitable for semiconductive memories includes a single SCR and a single transistor plus unique interconnections to provide a read-while-write array of such cells. The cell topology provides a small cell size with low stand-by power. The SCR pro-vides a memory function, while the single transistor provides an output function. In an alternative embodiment, a second transistor is employed for con-trolling writing into the cell.

Encapsulation package for a semiconductor element

Abstract: A semiconductor package device characterized by improved operation at ultra-high frequencies and by improved heat dissipation, includes an auxiliary metal stud mounted on a metal substrate. A semiconductor element, such as a field-effect transistor or bipolar transistor, is mounted on the auxiliary stud and has at least one electrode thereof electrically connected to the stud.

Oxide isolated integrated injection logic with selective guard ring

Abstract: A process for fabricating oxide-isolated vertical bipolar transistors and complementary oxide-isolated lateral bipolar transistors incorporates the steps of growing a doped epitaxial layer of single-crystal silicon on a silicon substrate, applying a first insulation material in a selected pattern over the epitaxial layer to define oxide-isolation regions and device regions, etching grooves in the areas in which oxide-isolation regions will be formed, applying a self-aligned base insulation material over those portions of the interface between the first insulation material and the grooves which bound the region between the base of any vertical bipolar transistor to be formed and the emitter of any lateral bipolar transistor to be formed, applying an impurity of a conductivity type opposite to the conductivity type of the epitaxial layer to those groove areas not covered by the self-aligned base insulation material, the impurity serving to prevent emitter-to-collector inversion along the wall of the base of any vertical bipolar transistor without shorting the emitter and collector of any lateral bipolar transistor, forming oxide-isolation regions in the grooves and forming the vertical bipolar transistors and the lateral bipolar transistors in the device regions. The process of the present invention will produce discrete lateral bipolar transistors, discrete vertical bipolar transistors capable of operation in the conventional mode or in the inverse mode, or a composite structure which merges both a vertical bipolar transistor and a lateral bipolar transistor together on the same silicon island to form an injection-logic gate in which the base of the vertical bipolar transistor serves as the collector of the lateral bipolar transistor, the vertical transistor being operated in the inverse mode.

Transistor amplifier with impedance matching transformer

Abstract: An amplifier includes a transistor and transformer having a primary winding and a tapped secondary winding The primary winding is connected in series between the input terminal and the transistor emitter The transistor base and one end of the secondary winding is grounded The other end of the secondary winding is connected to the transistor collector The transformer secondary tap is connected to an output terminal The ratio of that portion of the secondary turns connected between the tap and r-f ground and the primary turns is m The ratio of that portion of the secondary turns connected between the tap and the transistor collector and the primary turns is n For two-way impedance match between a source resistance Rs and a load resistance RL, n m2 (Rs/RL)-m-1

D.C. power source with temperature compensation

Abstract: An improved D. C. power source whose output voltage is independent of changes in temperature is disclosed. Compensation for changes in temperature is established by three features. For a change of the voltage drop in the forward direction between the base and the emitter of a transistor, a plurality of diodes provided in a bias circuit in the transistor are utilizied; for a change of the current amplification factor β of a transistor, an additional transistor is attached to the transistor, and; for a change of the value of an emitter resistor connected between the emitter of the transistor and the ground, an external stable resistor is utilized. The D. C. power source of the present invention is, in particular, useful for an integrated circuit.

Noise suppression circuit

Abstract: An improved noise suppression circuit which includes a first transistor having a collector, an emitter coupled to the input of the circuit, and a base coupled to an output of the circuit through an impedance means. The circuit includes a second transistor having a base coupled to the collector of the first transistor, a collector coupled to a reference potential, and an emitter integral with the impedance means. The circuit of the present invention can be constructed to suppress positive-going noise pulses, negative-going noise pulses, or one of each can be cascaded to suppress both positive and negative-going noise pulses.

Method of making metal oxide semiconductor devices

Abstract: A MOS transistor fabrication method using either three or four masking steps and wherein the channel between source and drain is defined by preferential etching of the semiconductor material resulting in a relatively deep V-shaped groove formed in the material between source and drain with the channel passing around this V-groove.

Monolithic semiconductor rectifier circuit structure

Abstract: A monolithic semiconductor rectifier circuit structure incorporating two npn power transistors and two Schottky-barrier diodes is disclosed. The transistors are connected in an inverted mode and are the main rectifying elements. The Schottky-barrier diodes are connected between the emitters and collectors of the respective transistors and help to initiate rapid turn-on of the transistors. The Schottky-barrier diodes have a relatively low forward voltage drop and their reverse recovery currents are substantially zero. Thus, the Schottky diodes operate with minimum power loss. The monolithic circuit structure may be combined with a discrete current transformer unit to form a hybrid rectifying circuit.