Showing papers on "Voltage-controlled oscillator published in 2022"

A Millimeter-Wave CMOS VCO Featuring a Mode-Ambiguity-Aware Multi-Resonant-RLCM Tank

Abstract: This paper presents a millimeter-wave NMOS-PMOS-complementary (CMOS) VCO with a multi-resonant Resistor-Inductor-Capacitor-Mutual Inductance (RLCM) tank. It features an 8-port multi-tap inductor with the switched-capacitor arrays to generate and align the 1 $^{{\text {st}}}$ , 2 $^{{\text {nd}}}$ and 3 $^{{\text {rd}}}$ harmonic resonances; all exhibit high impedance and high intrinsic quality factor to improve the absolute phase noise (PN) at both the flicker and thermal regions. The inductor of the RLCM tank introduces a metal resistor technique to fully prevent the mode-ambiguity issue during the VCO startup. Meanwhile, we first propose a detailed analysis of the upper and lower bound of the metal resistor, which is verified by the theoretical analysis, and circuit simulation. Prototyped in 65-nm CMOS technology, the VCO scores a PN_@1MHz down to −111.41 dBc/Hz with a power consumption of 11.1 mW at 1 V; it corresponds to a FOM_@1MHz up to 189.4 dBc/Hz over a 15.2% tuning range (24.62 to 28.66 GHz), while exhibiting a low 1/ $\text{f}^{3}$ PN corner between 480 to 730 kHz.

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

Abstract: This article demonstrates the potential of deep-subthreshold mixed-signal circuits in delivering medium-to-high performance to supply-constrained, energy-harvesting Internet of Things (IoT) sensing applications. This effort encapsulates the design and implementation of an ultra-low-voltage (ULV) 0.2-V open-loop VCO-based analog-to-digital converter (ADC). A replica VCO facilitates variation-aware VCO analog linearization. Analog phase-domain signal processing (APSP) techniques for beat-frequency extraction, phase-interpolation, and phase-folding relax constraints on both voltage-to-frequency analog circuitry and frequency-to-digital synchronous digital hardware. High-speed multi-phase frequency-to-digital converters (FDCs) and multi-rate digital back-end enable a sampling speed of 35 MS/s. The ADC prototype is implemented in 28-nm CMOS and achieves a peak SNDR of 64.4/59.9 dB, equivalent to an ENOB of 10.4/9.7 over 80-/160-kHz bandwidth (BW). The ADC core occupies an active area of 0.12 mm ² and consumes 15.9 $\mu \text {W}$ , resulting in a Walden and Schreier FoM of, respectively, 73.3/61.5 fJ/c-s and 161.4/159.9 dB at the corresponding BW configurations. Measurements across multiple ICs and supply voltages consolidate the value of variation-aware deep-subthreshold open-loop ADCs.

Methodology for Readout and Ring Oscillator Optimization Toward Energy-Efficient VCO-Based ADCs

Abstract: For the design of ring oscillator-based ADCs, little has been reported on how to optimally co-design the readout scheme and the ring oscillator core towards optimal energy efficiency. This paper describes a methodology to find this optimum for a target SQNR and signal bandwidth, for the case of 1st-order quantization noise shaping. In short, starting from initial assumptions on the VCO, the readout optimization boils down to finding the best VCO frequency. From this, the number of readout phases, the sampling frequency of the readout and the number of bits in the quantizers are derived. Then, it is explained how to adjust the VCO core toward the corresponding optimal VCO configuration. This is discussed for the case of a current-controlled ring oscillator, indicating the main constraints that define the design space for such a VCO optimization. If the actual VCO configuration is bounded by practical constraints, this approach can be re-iterated where a new readout optimization is performed taking these constraints into account.

A Low Phase Noise K-Band VCO With a Threshold Voltage-Based Current Source

Abstract: This letter presents a low-phase-noise voltage-controlled oscillator (VCO) with a threshold-voltage ( $V_{\mathrm {TH}}$ )-based current source. The proposed current source is insensitive to the supply voltage, and the flicker noise of the transistor in the current source is decoupled, leading to lower phase noise to the resonator. In addition, a small-size differential inductor is adopted to diminish the resonator loss and to increase the quality factor. Fabricated in a 130-nm CMOS technology, the proposed VCO demonstrates a tuning range of 23.8–26.3 GHz (10.4%). It achieved a phase noise of −74.73 dBc/Hz at 100 kHz and −107.36 dBc/Hz at 1 MHz offset frequencies from the 24.005-GHz carrier frequency, respectively. The figure of merit (FoM) reaches −188 dBc/Hz.

A Wide Tuning Range Low-Phase-Noise Ku/Ka Dual Bands SiGe VCO Based on Transformer-Coupled Tank

Abstract: A wide tuning range, low-phase-noise SiGe BiCMOS LC voltage-controlled oscillator (VCO) covering both the Ku- and Ka-bands is presented in this letter. The proposed VCO using a cross-coupled topology creates the fundamental harmonic from 14.35 to 17.86 GHz and the second harmonic, which is drawn from the common-mode point through a matched buffer, covering from 28.7 to 35.72 GHz. A transformer-coupled tank, which takes advantage of tank parasitics to create harmonic resonances, is used to reduce the phase noise (PN). The 5-bit binary-weighted capacitor bank is connected to the transformer secondary to create a wide tuning range, which is measured from 14.35 to 17.86 GHz (21.1%) and 28.7 to 35.72 GHz. Brilliant PN of −115.5 and −109 dBc/Hz at 1-MHz offset is measured at 14.53- and 29.1-GHz carrier frequencies individually. The proposed VCO with an extra output of the second harmonic exhibits little PN deterioration.

A Low-Jitter and Low-Spur Charge-Sampling PLL

Abstract: This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the reference spurs by both minimizing the modulated capacitance seen by the voltage-controlled oscillator (VCO) tank and by reducing the duty cycle of the sampling clock. A 50- $\mu \text{W}$ RF-dividerless frequency-tracking loop is also introduced to lock the CSPLL robustly when the VCO faces a sudden frequency disturbance. Fabricated in a 40-nm CMOS process, the prototype CSPLL occupies a core area of 0.13 mm ² and synthesizes 9.6-to-12-GHz tones using a 100-MHz reference. At 11.2 GHz, it achieves a reference spur of −77.3 dBc and an RMS jitter of 48.6 fs while consuming 5 mW.

Simulation-Based Optimization for Automated Design of Analog/RF Circuits

Abstract: Automation tools for circuit optimization have proven their usefulness in solving design issues by considering the technological aspects of downscaling. Recent advances have proven that the optimization method based on simulation is a powerful and important solution for the optimal sizing of electronic circuits. In this paper, we propose a simulation-based methodology for automatic optimization of the multi-objective design of an analog/RF circuit. As applications, we use both analog and RF circuits, respectively the LC tank Voltage Controlled Oscillator (VCO) and the new Current-Feedback Operational Amplifier (CFOA). For the LC-VCO, we optimize the power consumption and the phase noise. For the CFOA, we optimize its important performances such as bandwidth and parasitic resistances, for low-voltage, low-power applications. All simulations are performed by HSPICE using 0.13 µm RF CMOS and 0.18 µm CMOS technologies for the LC-VCO and the CFOA, respectively.

Design and Analysis of 55–63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS

Abstract: This article presents a 55–63-GHz fundamental multicore voltage-controlled oscillator (VCO) in a 28-nm bulk CMOS process. The single-core VCO utilizes stacking and magnetic coupling of two NMOS-based resonators, which increases the tank energy for phase noise reduction while maintaining low voltage swings for reliability. In the multi-core configuration, the oscillators are coupled in a way that also simplifies LO distribution toward the transmitter and receiver. The potential parasitic modes that occur both in single-core and multi-core configurations are suppressed by design. The implicit common-mode (CM) impedance control is utilized to reduce phase noise without any large extra tail inductor as used in a conventional complementary oscillator. The distributed nature of energy restoring elements in the proposed stacked oscillator also offers robust parasitic mode suppression compared to alternative implementation based on a conventional complementary oscillator. The working range of the prototype is between 55 and 63 GHz corresponding to a tuning range of 13.4% with power consumption varying from 15.3 to 12 mW across the tuning range. The prototype achieves the best phase noise of −95 and −121.7 dBc/Hz at 1- and 10-MHz offsets from the carrier at 55GHz. The corresponding peak figure of merits (FOMs) achieved are 178 and 185 dBc/Hz at 1- and 10-MHz offsets from the carrier.

FR4-Based Low Phase Noise SISL VCO Using Tunable Weakly Coupled Resonators

Abstract: In this letter, a voltage-controlled oscillator (VCO) with low cost, wide-tuning range, and low phase noise is proposed based on substrate integrated suspended line (SISL) technology. Benefiting from the weak coupling between half-wavelength resonators, the $Q$ value can be improved, so as to reduce the phase noise of the VCO. By introducing a varactor in the high- $Q$ resonator, a wide-tuning range is achieved. All the used boards choose FR4 material with very low cost. The designed SISL VCO has a tuning range of 380 MHz and has a phase noise of −122.81 dBc/Hz at a 1-MHz offset relative to the 5.88-GHz carrier. Compared with the existing board-level VCOs, this design features a wide-tuning range and low phase noise based on a low-cost platform.

A 1.15-mW Low-Power Low-Complexity Reconfigurable FM-UWB Transmitter

Abstract: A 1.15-mW 3.75–4.25-GHz frequency-modulated ultrawideband (FM-UWB) transmitter (TX) is fabricated in 65-nm CMOS, with digitally reconfigurable subcarrier frequencies, UWB bandwidth, and radio frequency (RF) frequency band. Low-complexity submodules are utilized with significant power savings. An ultralow-current hybrid module is for bandgap reference (BGR) and power-ON reset (POR), and a single-ended crystal oscillator (XO) generates a 12-MHz clock reference. A dual-path ring voltage-controlled oscillator (VCO) conducts linear RF FM, followed by a push–pull power amplifier (PA) for 100-kb/s wireless data transmission. A differential relaxation oscillator (OSC) is for subcarrier generation, and an intermittent dual-mode frequency calibration loop ensures system robustness. Experimental results show that the presented FM-UWB TX successfully generates an Federal Communications Commission (FCC)-compliant UWB signal, with an energy efficiency of 11.5 nJ/bit and an active area of 0.21 mm² from a 1-V supply. The 2.25- $\mu \text{A}$ hybrid BGR and POR achieves a temperature coefficient of 32 ppm/°C, a line regulation of 2.3%/V, a supply-ramp-rate-tolerant power-ON, and brown-out function. The 40- $\mu \text{W}$ XO features a low-frequency inaccuracy of 4 ppm/V. The 40- $\mu \text{A}$ relaxation OSC provides the reconfigured two-frequency shift keying (FSK) triangular amplitude and frequency. The 2.79–5.18-GHz 0.6-mW ring VCO is capable of providing the phase noise performance of −77 dBc/Hz at the 1-MHz offset, followed by the 0.45-mW PA having the output power higher than −14 dBm and the peak power-added efficiency (PAE) of 29.6%. All these benefit low-power low-cost TX implementation, where the carrier and subcarrier frequencies are calibrated by an intermittent digital loop with omitted power dissipation.

A 196.5 dBc/Hz FOMT 16.8–21.6-GHz Class-F23 CMOS VCO With Transformer-Based Optimal Q-Factor Tank

Abstract: This letter presents an optimal tank- $Q$ Class-F₂₃ voltage-controlled oscillator (VCO) in 65-nm CMOS. The $Q$ -factor of the transformer-based multi-LC resonator is maximized in the Class-F operation mode by the proposed graphical $Q$ -optimization method. The frequency tuning range (TR) is expanded by 26% as well. The phase noise (PN) is improved by reshaping the impulse sensitivity function (ISF) with the 2^nd and 3^rd harmonic tuning. Occupying 0.112 mm², the VCO at 16.8 GHz exhibits −112.2 dBc/Hz PN at 1 MHz offset and 196.5 dBc/Hz $\text{FOM}_{T}$ at 10 MHz offset. The measured TR is 25% (16.8–21.6 GHz). The oscillator core consumes 7 mW at 1 V supply.

Digital Low-Dropout Regulator With Voltage-Controlled Oscillator Based Control

Abstract: A digital low-dropout (DLDO) regulator is described which is controlled by voltage-controlled oscillator (VCO) based feedback loop. There are two VCOs in the control loop whose frequencies are controlled by the output voltage and reference level, respectively. By comparing the phase between the output clocks of the two VCOs and modulating the number of enabled power transistors and their on -times, the output voltage is regulated. The proposed VCO-based control is a hybrid of digital and analog control schemes because the number of enabled power transistors is controlled in discrete step while the on -time is modulated continuously. In order to improve the transient speed, transient detector is employed in the DLDO regulator. The DLDO regulator with the proposed VCO-based control has been implemented in a 65-nm CMOS process. The DLDO regulator can provide the output from 0.5 to 1.1 V from the input ranging from 0.9 to 1.2 V. The load transient time is smaller than 90 ns for both step-up and step-down changes of load current. The peak current efficiency is 99.3%.

OTA-Free 1–1 MASH ADC Using Fully Passive Noise-Shaping SAR & VCO ADC

Abstract: We present an OTA-free 1–1 multi-stage noise-shaping (MASH) analog-to-digital converter (ADC) utilizing a fully passive noise-shaping successive approximation register (NS-SAR) as the first stage and an open-loop ring voltage-controlled oscillator (VCO) as the second stage. The key contribution of this work is to address the challenge of driving large sampling capacitors for high-resolution NS-SAR. The proposed architecture allows a low-resolution NS-SAR stage and leverages residue attenuation due to passive charge sharing in the NS-SAR to linearize the VCO. The MASH architecture suppresses quantization noise and SAR comparator noise at the ADC output, and the high pass shapes VCO thermal noise. In addition, we demonstrate a computationally inexpensive foreground inter-stage gain calibration algorithm for the proposed ADC architecture. The prototype ADC consumes 0.16 mW while achieving an SNDR/DR of 71.5/75.8 dB over a 1.1-MHz bandwidth and Walden FoM of 23.3 fJ/step, which is the lowest in 65-nm technology.

Linearity Improvement of VCO-Based ADC via Complementary Bias Voltage Control for IoT Devices

Abstract: Ring-VCO (Voltage controlled oscillator)-based ADCs are suitable for the data acquisition in embedded sensors which are at the core of AI enabled IoT (Internet of Things) devices. Fundamentally, the ring-VCO can generate digital code by counting frequency from its voltage-controlled oscillation. However, the ring-VCO has some issues related to non-linearity and power dissipation due to the voltage-to-frequency (V-to-F) tuning characteristics. Particularly, for low power operation with low voltage supply, the linearity further degrades. This paper presents a complementary bias voltage control approach to attain a linear V-to-F characteristics with low-power dissipation. The novel voltage-to-current (V-to-I) conversion provides the linear bias current source and sink matching for current-starved inverter-based delay elements. Furthermore, the proposed circuit can be extended to optimize nonlinearity error by selecting an optimal transistor size. Simulation results with a 0.5V power supply circuit designed in TSMC 180nm CMOS technology shows that maximum nonlinearity error is below 0.24% for 4-stage and below 0.49% for 8-stage ring-VCO.

A 48 GHz Fundamental Frequency PLL with Quadrature Clock Generation for 60 GHz Transceiver

Abstract: This paper presents a design of a 48 GHz CMOS phase-locked loop (PLL) for 60 GHz millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, a fundamental frequency PLL with quadrature clock generation scheme is proposed. Specifically, with an implicit capacitive-bridged shunt peaking network, a second order harmonic filtering technique is realized in the voltage control oscillator (VCO) to broaden the bandpass response, thereby avoiding the complex common-mode resonant tank calibration and improving the phase noise performance. A robust current mode logic (CML) static frequency divider topology is adopted to realize the prescaler and to generate the quadrature clock. With the capacitive-bridged shunt peaking load and robust biasing circuit, the static frequency divider locking range and high frequency performance is improved and its reliability is enhanced over the PVT corners. To improve the image suppression ratio of the transceiver, a quadrature clock phase calibration scheme is proposed and verified. Fabricated in a 65 nm CMOS process, the PLL occupies a core area of 800 μm × 950 μm. Over the frequency range of 45.2 to 52.6 GHz, the measured PLL in-band phase noise PLL is better than −90 dBc/Hz@100 KHz offset, and its jitter is less than 155 fs. Moreover, the reference spur is less than −60 dBc/Hz.

A Swing-Enhanced Class-D VCO Using a Periodically Time-Varying (PTV) Inductor

Abstract: This letter reports the design and analysis of a swing-enhanced class-D voltage-controlled oscillator (VCO) utilizing a periodically time-varying (PTV) inductor to boost the output swing that effectively improves the phase noise (PN) in both $1/f^{2}$ and $1/f^{3}$ regions at a low supply voltage ( $V_{\mathrm{ DD}}$ ). Without extra switches, the PTV inductor reuses the original cross-coupled transistors in the class-D oscillator that semiperiodically cancels the magnetic flux between two coupled inductors. Fabricated in 65-nm LP CMOS, the 3.67-to-4.43-GHz VCO prototype measures figure of merits of 192.4 ± 1.5 dBc/Hz at 1-MHz offset frequency and 194.4 ± 0.8 dBc/Hz at 10-MHz offset frequency when the $V_{\mathrm{ DD}}$ varies from 0.3 to 0.4 V.

A 4.4μW 2.5kHz-BW 92.1dB-SNDR 3^rd-Order VCO-Based ADC With Pseudo Virtual Ground Feedforward Linearization

Abstract: The rise of the internet-of-things and distributed sensor nodes with machine-learning and edge processing are driving the need for low-power, high-precision ADCs. These highly digital systems are best implemented in advanced process nodes that have low intrinsic gain and low supply voltages, making the design of the high-performance amplifiers required in high-precision delta-sigma (ΔΣ) ADCs challenging. Time-domain ADC architectures, such as voltage-controlled oscillator (VCO)-based ADCs, have been explored to address these challenges as time-domain processing is agnostic to supply voltage and benefits from advanced process nodes with faster switching times [1]. However, linearity has been challenging as open-loop VCO-based ADCs have only ~50dB SFDR. As such, significant research has been devoted to the development of linearization techniques such as feedback [1], mixed-domain operation [2], digital calibration [3], and higher-order noise-shaping using VCO-only architectures [4]. This paper presents a 3 ^rd -order, VCO-only ΔΣ ADC achieving 92.1dB SNDR over a 2.5kHz bandwidth (BW) using a pseudo virtual ground feedforward (PVG FF) technique. The key concept is to feed forward the pseudo virtual ground in a capacitively coupled VCO-based ADC, which linearizes and stabilizes the system while only using a single feedback DAC. This approach enables a high dynamic range (DR) due to the 3 ^rd -order noise-shaping and >120dB SFDR due to the linearization. The prototype ADC consumes 4.4μW from a 0.8V supply achieving the best-reported SNDR Schreier figure of merit (FoM) for VCO-based ADCs at 179.6dB.

An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector

Abstract: This work presents an ultra-low jitter, direct $W$ -band phase-locked loop (PLL). Using the proposed power-gating injection-locked frequency multiplier (PG-ILFM)-based phase detector (PD) that can maintain a high phase-error-detection gain even at high frequencies above 100 GHz, this $W$ -band PLL can achieve a very low in-band phase noise. Due to this intrinsically low in-band phase noise, the bandwidth of the PLL can be extended so that it can suppress the poor phase noise of the $W$ -band voltage-controlled oscillator (VCO). The frequency-offset canceller (FOC) is also presented to remove the possible frequency offset between the main VCO of the PLL and the replica VCO of the PG-ILFM-based PD. Operating in the background, the FOC can ensure high phase-error-detection gain and wide loop bandwidth and, thus, the low-jitter performance of the PLL. The proposed PLL was fabricated in a 65-nm CMOS process, and it used a power of 22.5 mW and an area of 0.16 mm ² . The rms jitter, integrated from 1 kHz to 300 MHz, was 82 fs at 102 GHz. It also achieved the FoM _JIT of–248.2 dB, which is the best among the state-of-the-art $W$ -band frequency synthesizers.

A 78.8–84 GHz Phase Locked Loop Synthesizer for a W-Band Frequency-Hopping FMCW Radar Transceiver in 65 nm CMOS

Abstract: A W-band integer-N phase-locked loop (PLL) for a frequency hopping frequency modulation continuous wave (FMCW) radar is implemented in 65-nm CMOS technology. The cross-coupled voltage-controlled oscillator (VCO) was designed based on a systematic analysis of the VCO combined with its push-pull buffer to achieve high efficiency and high output power. To provide a frequency hopping functionality without any overhead in the implementation, the center frequency of the VCO is steeply controlled by the gate voltage of the buffer, which effectively modifies the susceptance of the VCO load. A stand-alone VCO with the proposed architecture is fabricated, and it achieves an output power of 13.5 dBm, a peak power efficiency of 9.6%, and a tuning range of 3.5%. The phase noise performance of the VCO is −92.6 dBc/Hz at 1-MHz and −106.1 dBc/Hz at 10 MHz offset. Consisting of a third-order loop filter and a divider chain with a total modulus of 48, the locking range of the implemented PLL with the cross-coupled VCO is recorded from 78.84 GHz to 84 GHz, and its phase noise is −85.2 dBc/Hz at 1-MHz offset.

Measurement of electromagnetic field immunity of voltage-controlled oscillator-based analog-to-digital converters in 28 nm CMOS technology

Abstract: Internet-of-Things (IoT) devices are compact and low power. A voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) benefits from scaled CMOS transistors in representing analog signals in the time domain and therefore meets those demands. However, we find the potential drawback of VCO-based ADCs for the electromagnetic susceptibility (EMS) to RF disturbances that are essentially present in an IoT environment. It is exhibited that the single and even differential designs of VCO-based ADC suffer from the EMS by RF disturbance, which behaves differently from the known common-mode noise rejection. A 28 nm CMOS 11-bit VCO-ADC prototype exhibits sensitivity against RF signals in the widely used 2.4 GHz frequency band.

Potential Loading of Virgin Coconut Oil into Centrifugally‐Spun Nanofibers for Biomedical Applications

Abstract: Virgin coconut oil (VCO) has become a multifunctional material for biomedical applications due to its remarkable health benefits. The use of VCO for biomedical applications has seen tremendous growth over recent years, triggering researchers to develop various approaches for VCO utilization. Nanofibers-based structure offers promising properties to encapsulate VCO, enhancing its performance and broadening its application in the medical field. Studies of VCO-loaded polymeric nanofibers for biomedical applications are currently gradually rising. Recently, in nanofibers technology, centrifugal jet spinning (CJS) offers cost-efficient and higher production rates to yield nanofibers compared to the other methods. This review summarizes recent advances of VCO for biomedical applications. Comprehensive suggestions for encapsulating VCO into nanofibers using the CJS technique are also provided. Highlights of future challenges in utilizing the CJS technique to produce VCO-loaded nanofibers for biomedical applications are also elaborated.

A 24 GHz FMCW/Doppler Dual-Mode Frequency Synthesizer With 68.8 kHz RMS FM Error and 1.25 GHz Chirp Bandwidth

Abstract: This brief presents a 24 GHz dual-mode frequency synthesizer designed in a 55-nm CMOS technology supporting both Doppler and frequency modulated continuous wave (FMCW) radars. The effects of chirp linearity and delta-sigma modulation (DSM) resolution on the rms FM error is analyzed. A design procedure for the PLL loop bandwidth and time interval of the frequency step to reduce the rms FM error is proposed. A voltage-controlled oscillator (VCO) featuring a four-coil transformer load is developed providing differential local oscillation (LO) signals for the transmitter (TX) and quadrature LO signals for the 2-channel receiver (RX). The prototype is designed with a loop bandwidth of 350 kHz, a frequency step time interval of $2 ~\mu s$ , and a VCO tuning linearity of 26%. In the FMCW mode, it achieved an rms FM error of 68.8 kHz over a 1.25 GHz chirp bandwidth. In the Doppler mode, the VCO operates in the free-running mode to save power consumption. An 8-bit digital-to-analog converter (DAC) is used to provide the VCO control voltage compensating process and voltage variations. The free-running VCO operates at a 24.125 GHz and has a frequency error of less than 1 MHz.

Efficacy of Transmission Poles Characteristics on K-Band VCOs Phase Noise Reduction

Abstract: In this paper, effectiveness of multi-resonance around the parallel resonance of an LC-tank circuit on the reduction of K-band Voltage-Controlled Oscillators (VCOs) phase noise is proposed. The skirt characteristics of the Scattering $(\vert \mathrm{S}\vert)$ parameters of the resonators is sharpened by introducing transmission poles beside the parallel resonance of the LC-tank circuit. In return, an enhanced the resonator loaded quality (Q) factor without compromising the unloaded Q-factor is obtained. Three designs are realized, verified and compared to the others in a differential VCO topology and the phase noise reduction in post-layout simulations is confirmed. Finally, two chips are fabricated in $0.18-\upmu \mathrm{m}$ CMOS technology and measured.