C
C. Kenyon
Researcher at Intel
Publications - 7
Citations - 3607
C. Kenyon is an academic researcher from Intel. The author has contributed to research in topics: PMOS logic & NMOS logic. The author has an hindex of 7, co-authored 7 publications receiving 3364 citations.
Papers
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Proceedings ArticleDOI
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell
P. Bai,C. Auth,Sridhar Balakrishnan,M. Bost,Ruth A. Brain,V. Chikarmane,R. Heussner,Makarem A. Hussein,Jack Hwang,D. Ingerly,R. James,J. Jeong,C. Kenyon,E. Lee,Seung Hwan Lee,Nick Lindert,Mark Y. Liu,Z. Ma,T. Marieb,Anand Portland Murthy,Ramune Nagisetty,Sanjay Natarajan,J. Neirynck,Andrew Ott,C. Parker,J. Sebastian,R. Shaheed,Swaminathan Sivakumar,Joseph M. Steigerwald,S. Tyagi,Cory E. Weber,Bruce Woolery,Yeoh Andrew W,Kevin Zhang,M. Bohr +34 more
TL;DR: A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented in this article.
Proceedings ArticleDOI
An advanced low power, high performance, strained channel 65nm technology
S. Tyagi,C. Auth,P. Bai,G. Curello,H. Deshpande,S. Gannavaram,Oleg Golonzka,R. Heussner,R. James,C. Kenyon,Seok-Hee Lee,Nick Lindert,Mark Y. Liu,Ramune Nagisetty,Sanjay Natarajan,C. Parker,J. Sebastian,Sell Bernhard,Swaminathan Sivakumar,A. St. Amour,K. Tone +20 more
TL;DR: In this article, an advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented at 1V and off current of 100nA/mum.