S
S. Gannavaram
Researcher at Intel
Publications - Â 5
Citations - Â 321
S. Gannavaram is an academic researcher from Intel. The author has contributed to research in topics: Logic gate & Transistor. The author has an hindex of 5, co-authored 5 publications receiving 313 citations.
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Proceedings ArticleDOI
A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications
C.-H. Jan,M. Agostinelli,M. Buehler,Zhanping Chen,S.-J. Choi,G. Curello,H. Deshpande,S. Gannavaram,Hafez Walid M,U. Jalan,M. Kang,Pramod Kolar,K. Komeyli,B. Landau,A. Lake,N. Lazo,Seung Hwan Lee,T. Leo,J. Lin,Nick Lindert,S. Ma,L. McGill,C. Meining,A. Paliwal,Joodong Park,K. Phoa,Ian R. Post,N. Pradhan,M. Prince,Abdur Rahman,J. Rizk,L. Rockford,G. Sacks,A. Schmitz,H. Tashiro,Curtis Tsai,P. Vandervoorn,J. Xu,L. Yang,J.-Y. Yeh,J. Yip,Kevin Zhang,Yuegang Zhang,P. Bai +43 more
TL;DR: The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently.
Proceedings ArticleDOI
An advanced low power, high performance, strained channel 65nm technology
S. Tyagi,C. Auth,P. Bai,G. Curello,H. Deshpande,S. Gannavaram,Oleg Golonzka,R. Heussner,R. James,C. Kenyon,Seok-Hee Lee,Nick Lindert,Mark Y. Liu,Ramune Nagisetty,Sanjay Natarajan,C. Parker,J. Sebastian,Sell Bernhard,Swaminathan Sivakumar,A. St. Amour,K. Tone +20 more
TL;DR: In this article, an advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented at 1V and off current of 100nA/mum.
Proceedings ArticleDOI
A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications
Ian R. Post,Muhammad Akbar,G. Curello,S. Gannavaram,Hafez Walid M,U. Jalan,K. Komeyli,J. Lin,Nick Lindert,Joodong Park,J. Rizk,G. Sacks,C. Tsai,D. Yeh,P. Bai,C.-H. Jan +15 more
TL;DR: In this article, a 65nm CMOS technology (29nm Lgate, 210nm pitch) employing uni-axial strained silicon transistors was used to achieve record-breaking performance with fT/fMAX values of 238 GHz/295 GHz.
Proceedings ArticleDOI
A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors
C.-H. Jan,P. Bai,S. Biswas,M. Buehler,Zhanping Chen,G. Curello,S. Gannavaram,Hafez Walid M,Jun He,J. Hicks,U. Jalan,N. Lazo,J. Lin,Nick Lindert,C. Litteken,M. Jones,M. Kang,K. Komeyli,A. Mezhiba,S. Naskar,S. Olson,Joodong Park,Rachael J. Parker,L. Pei,Ian R. Post,N. Pradhan,Chetan Prasad,M. Prince,J. Rizk,G. Sacks,H. Tashiro,D. Towner,C. Tsai,Yih Wang,L. Yang,J.-Y. Yeh,J. Yip,Kaizad Mistry +37 more
TL;DR: A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products.
Proceedings ArticleDOI
Reliability studies on a 45nm low power system-on-chip (SoC) dual gate oxide high-k / metal gate (DG HK+MG) technology
Chetan Prasad,P. Bai,S. Gannavaram,Hafez Walid M,J. Hicks,C.-H. Jan,J. Lin,M. Jones,K. Komeyli,Roza Kotlyar,Kaizad Mistry,Ian R. Post,Curtis Tsai +12 more
TL;DR: In this article, the authors present extensive reliability characterization results for a dual-gate 45nm HK+MG technology, where BTI, HCI and TDDB degradation modes on the Logic and I/O transistors are studied and excellent reliability is demonstrated.