Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

/pdf/high-k-gate-dielectrics-current-status-and-materials-zjvba0c4u8.pdf

High-κ gate dielectrics: Current status and materials properties considerations

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

/pdf/fundamentals-of-modern-vlsi-devices-471xd7l9pf.pdf

Fundamentals of Modern VLSI Devices

While there has been growing interest in two-dimensional (2-D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancy due to the lack of a complete picture of their performance potential. The focus of this article is on contacts. We demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2-D material can be harvested. Using scandium contacts on 10-nm-thick exfoliated MoS2 flakes that are covered by a 15 nm Al2O3 film, high effective mobilities of 700 cm2/(V s) are achieved at room temperature. This breakthrough is largely attributed to the fact that we succeeded in eliminating contact resistance effects that limited the device performance in the past unrecognized. In fact, the apparent linear dependence of current on drain voltage had mislead researchers to believe that a truly Ohmic contact had already been achieved, a miscon...

/pdf/high-performance-multilayer-mos2-transistors-with-scandium-4l4zqklvyi.pdf

High Performance Multilayer MoS2 Transistors with Scandium Contacts

Electrically induced electron-spin polarization near the edges of a semiconductor channel was detected and imaged with the use of Kerr rotation microscopy The polarization is out-of-plane and has opposite sign for the two edges, consistent with the predictions of the spin Hall effect Measurements of unstrained gallium arsenide and strained indium gallium arsenide samples reveal that strain modifies spin accumulation at zero magnetic field A weak dependence on crystal orientation for the strained samples suggests that the mechanism is the extrinsic spin Hall effect

https://science.sciencemag.org/content/sci/306/5703/1910.full.pdf

Observation of the spin Hall effect in semiconductors.

Wide-band-gap oxides such as SrTiO3 are shown to be critical tests of theories of Schottky barrier heights based on metal-induced gap states and charge neutrality levels. This theory is reviewed and used to calculate the Schottky barrier heights and band offsets for many important high dielectric constant oxides on Pt and Si. Good agreement with experiment is found for barrier heights. The band offsets for electrons on Si are found to be small for many key oxides such as SrTiO3 and Ta2O5 which limit their utility as gate oxides in future silicon field effect transistors. The calculations are extended to screen other proposed oxides such as BaZrO3. ZrO2, HfO2, La2O3, Y2O3, HfSiO4, and ZrSiO4. Predictions are also given for barrier heights of the ferroelectric oxides Pb1−xZrxTiO3 and SrBi2Ta2O9 which are used in nonvolatile memories.

Band offsets of wide-band-gap oxides and implications for future electronic devices

The observation of single interface traps in small area MOSFET's by charge pumping is demonstrated for the first time, The dependence of the single trap charge pumping current on the base level voltage is described, Also the creation of one single interface trap under influence of low level hot carrier injection is demonstrated. A prediction of the charge pumping current behavior as a function of rise and fall time and temperature for the case of individual traps is made. The correlation with RTS-noise experiments is discussed.

Observation of single interface traps in submicron MOSFET's by charge pumping

The nucleation and preferential orientation of Lead Zirconate-Titanate (PZT) films deposited by sol-gel spin-coating on Pt bottom electrodes is discussed. The crucial role of the Ti adhesion layer is highlighted. A qualitative crystallization model is presented which can explain the nucleation behavior of PZT-films with different Zr/Ti-ratios on different electrode structures as well as the preferential orientation of the PZT-film.

Nucleation and orientation of sol-gel pzt-films on pt electrodes

A fast and simple method has been introduced to calculate the time-to-breakdown t/sub BD/ in ultra-thin gate oxides. This method is based on monitoring the increase in the current during stress. This new method allows one to determine the maximum voltage at which a gate oxide will comply with 10 year lifetime, taking into account both t/sub BD/-spread and area dependence.

A fast and simple methodology for lifetime prediction of ultra-thin oxides

In this study the field acceleration of intrinsic and extrinsic breakdown is studied. For the intrinsic mode an exp(1/E)-acceleration law is found, while for the extrinsic mode an new exp(E)-acceleration law for Q/sub BD/ is proposed. This field acceleration model is implemented in a maximum likelihood algorithm together with a new analytical expression for fitting competing Weibull distributions. With this algorithm an extensive t/sub BD/-data set measured at different stress conditions can be fitted excellently in one single calculation. From the result, predictions of low-field oxide reliability are made and the screening conditions in order to guarantee a pre-set reliability specification are calculated.

On the field dependence of intrinsic and extrinsic time-dependent dielectric breakdown

A continued fast interface trap generation is observed in n-channel MOS transistors after termination of the hot-carrier stress. The magnitude of this post-stress effect is strongly dependent on the conditions of the preceding stress, on the post-stress conditions and on the process parameters. For measurements at 293 K, a simple model is proposed which is based on the release of hydrogen by the thermal detrapping of holes, and which can explain the observed dependencies. The importance of the post-stress D/sub it/-generation is illustrated for the case of dynamic stress conditions where it can lead to an apparently deviating degradation behavior. >

Herman Maes

Papers

Observation of single interface traps in submicron MOSFET's by charge pumping

Nucleation and orientation of sol-gel pzt-films on pt electrodes

A fast and simple methodology for lifetime prediction of ultra-thin oxides

On the field dependence of intrinsic and extrinsic time-dependent dielectric breakdown

On the hot-carrier-induced post-stress interface trap generation in n-channel MOS transistors