Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

While there has been growing interest in two-dimensional (2-D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancy due to the lack of a complete picture of their performance potential. The focus of this article is on contacts. We demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2-D material can be harvested. Using scandium contacts on 10-nm-thick exfoliated MoS2 flakes that are covered by a 15 nm Al2O3 film, high effective mobilities of 700 cm2/(V s) are achieved at room temperature. This breakthrough is largely attributed to the fact that we succeeded in eliminating contact resistance effects that limited the device performance in the past unrecognized. In fact, the apparent linear dependence of current on drain voltage had mislead researchers to believe that a truly Ohmic contact had already been achieved, a miscon...

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High Performance Multilayer MoS2 Transistors with Scandium Contacts

Electrically induced electron-spin polarization near the edges of a semiconductor channel was detected and imaged with the use of Kerr rotation microscopy The polarization is out-of-plane and has opposite sign for the two edges, consistent with the predictions of the spin Hall effect Measurements of unstrained gallium arsenide and strained indium gallium arsenide samples reveal that strain modifies spin accumulation at zero magnetic field A weak dependence on crystal orientation for the strained samples suggests that the mechanism is the extrinsic spin Hall effect

https://science.sciencemag.org/content/sci/306/5703/1910.full.pdf

Observation of the spin Hall effect in semiconductors.

Wide-band-gap oxides such as SrTiO3 are shown to be critical tests of theories of Schottky barrier heights based on metal-induced gap states and charge neutrality levels. This theory is reviewed and used to calculate the Schottky barrier heights and band offsets for many important high dielectric constant oxides on Pt and Si. Good agreement with experiment is found for barrier heights. The band offsets for electrons on Si are found to be small for many key oxides such as SrTiO3 and Ta2O5 which limit their utility as gate oxides in future silicon field effect transistors. The calculations are extended to screen other proposed oxides such as BaZrO3. ZrO2, HfO2, La2O3, Y2O3, HfSiO4, and ZrSiO4. Predictions are also given for barrier heights of the ferroelectric oxides Pb1−xZrxTiO3 and SrBi2Ta2O9 which are used in nonvolatile memories.

Band offsets of wide-band-gap oxides and implications for future electronic devices

A low voltage, high performance 0.35 ?m embedded flash EEPROM cell technology

A novel approach to monolithic pixel detectors based on SOI (silicon-on-insulator) wafers with high-resistivity substrates is being pursued by the CERN RD-19 collaboration. The authors report the results of electrical evaluation measurements performed on the devices fabricated in the substrate. The SOI preparation processes considered (SIMOX and laser or stripheater ZMR) appear to be compatible with the fabrication of detectors of suitable quality in the high-resistivity substrate. With reference to the detecting elements in the substrate, ZMR wafers give very good results. For SIMOX wafers, the main concern seems to be the higher depletion voltage resulting from the increase in effective doping concentration. >

Detector diodes and test devices fabricated in high resistivity SOI wafers

The intensity profiles of various kinds of topheaters are compared and discussed. Using the mercury-arc lamp heater experiments on polycrystalline silicon layers of thicknesses varying from 1 to 10 urn were performed. The 10 fiva layers were polished prior to recrystallization. After zone melting recrystallization they showed a strong (100) texture combined with an alignment of the [010] direction with the scan direction. By patterning 1 ¼m poly-silicon films into isolated narrow silicon stripes, the kinetic mechanism that is shown to be responsible for the alignment of the [010] direction along the scan direction could be inhibited. In this way other mechanisms that influence the orientation could be studied. Finally some electrical characteristics are presented.

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S1946427400566159

Evaluation of Lamp Zone-Melting Recrystallization

Characterization of LPCVD Silicon Oxynitride Films

Raman spectroscopy is used to study crystal damage and electrical damage in n + -GaAs produced by reactive ion etching (REE). H 2 RIE is compared with CH 4 /H 2 RIE and the effect of temperature annealing is studied. The results are compared with C-V analysis. It is found that structural damage introduced by RIE in the surface layers of the sample is larger for the H 2 plasma than for the CH 4 /H 2 plasma. Annealing results in a decrease of this structural damage. H 2 RIE as well as CH 4 /H 2 RIE cause an increase of the inactive surface region. This increase is found to be larger for the H 2 RDE. C-V experiments show that annealing results in a reactivation and associated decrease of the width of the inactive region.

Herman Maes

Papers

A low voltage, high performance 0.35 ?m embedded flash EEPROM cell technology

Detector diodes and test devices fabricated in high resistivity SOI wafers

Evaluation of Lamp Zone-Melting Recrystallization

Characterization of LPCVD Silicon Oxynitride Films

Raman Spectroscopy Study of Damage in n+ - GaAs Introduced by H2 and CH4/H2 RIE