H
Herman Maes
Researcher at Katholieke Universiteit Leuven
Publications - 310
Citations - 10763
Herman Maes is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Silicon & Field-effect transistor. The author has an hindex of 47, co-authored 310 publications receiving 10503 citations. Previous affiliations of Herman Maes include Siemens & Alcatel-Lucent.
Papers
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Stress induced charge trapping effects in SiO2/Al2O3 gate stacks with TiN electrodes
TL;DR: In this article, strong polarity dependent charge trapping effects have been observed in as-deposited SiO2/Al2O3 gate stacks with TiN gate electrodes on n- and p-type Si substrates using current voltage and capacitance voltage measurements.
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Direct and post-injection oxide and interface trap generation resulting from low-temperature hot-electron injection
TL;DR: In this article, direct and post-injection trap generation, induced by low-temperature (∼77 K) hot-electron injection, has been studied, where the main degradation mechanism attributed to the release, migration, and subsequent reaction of a hydrogenic species is inoperative, not only due to the suppressed release but also to the freeze-out of the species motion.
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Determining weak Fermi-level pinning in MOS devices by conductance and capacitance analysis and application to GaAs MOS devices
Koen Martens,Wenfei Wang,A. Dimoulas,Gustaaf Borghs,Marc Meuris,Guido Groeseneken,Herman Maes +6 more
TL;DR: In this article, a straightforward methodology is presented to distinguish the presence of large amounts of interface traps causing weak Fermi-level pinning from other effects in MOS capacitors based on GaAs or other alternative semiconductors.
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Influence of Zr/Ti ratios on the deformation in the hysteresis loop of Pb(Zr,Ti)O3 thin film capacitors
TL;DR: In this article, a large field shift and a constriction in the hysteresis loops of Pb(Zr,Ti)O3 thin film capacitors with various Zr/Ti ratios were studied as a function of the annealing temperature after patterning the top sputter-deposited Pt electrode using reactive ion etch with Ar gas.
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A 5 V-compatible flash EEPROM cell with microsecond programming time for embedded memory applications
J. Van Houdt,Dirk Wellekens,L. Faraone,Luc Haspeslagh,Ludo Deferm,Guido Groeseneken,Herman Maes +6 more
TL;DR: In this article, a split-gate flash EEPROM cell that relies on enhanced hot-electron injection onto the floating gate for fast 5 V-only programming is presented.