Herman Maes

TL;DR: In this paper, the authors reviewed the techniques and methodologies to be applied in R&D laboratories for the assessment of thin gate dielectrics reliability and hot carrier degradation and how the application of these techniques allows to obtain a better insight in the physics of the degradation process.

TL;DR: In this paper, an alternative device architecture for improved hot carrier reliability based on the GOLD concept is proposed, where the gate overlap is accurately controlled independently of the implant conditions, and a comparison with LDD devices shows a large improvement in resistance against hot-carrier degradation with this new device architecture.

TL;DR: In this paper, it was shown that not only the gate current noise, but also the substrate current noise largely increase at the soft-breakdown moment in n-channel metal-oxide-semiconductor field effect transistor (nMOSFET) stressed with positive gate polarity.

TL;DR: In this article, the backward adaptive conservative methodology is step by step replaced by a methodology considering the ESD issue already during process development and involving more predictive ESD-TCAD into the development cycle.

TL;DR: A comparison of several different programming mechanisms utilised to store Multilevel information on a specifc device shows that Source Side Injection (SSI) is indeed a very viable approach for Multi-Level Charge Storage (MLCS) which could be applied without requiring program verify.