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Indranil Chatterjee

Researcher at University of Bristol

Publications -  41
Citations -  809

Indranil Chatterjee is an academic researcher from University of Bristol. The author has contributed to research in topics: Soft error & Leakage (electronics). The author has an hindex of 14, co-authored 41 publications receiving 673 citations. Previous affiliations of Indranil Chatterjee include Vanderbilt University & Airbus Defence and Space.

Papers
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Journal ArticleDOI

“Leaky Dielectric” Model for the Suppression of Dynamic $R_{\mathrm{ON}}$ in Carbon-Doped AlGaN/GaN HEMTs

TL;DR: In this article, the authors identify the causes of dynamic dispersion using substrate bias ramps to isolate the leakage paths and trapping locations in the epitaxy and simulation to identify their impact on the device characteristics.
Proceedings ArticleDOI

Impact of buffer leakage on intrinsic reliability of 650V AlGaN/GaN HEMTs

TL;DR: In this article, the role of buffer traps (identified as CN acceptors through current DLTS) in the off-state leakage and dynamic Ron of 650V rated GaN-on-Si power devices is investigated.
Journal ArticleDOI

Impact of Technology Scaling on SRAM Soft Error Rates

TL;DR: In this paper, the authors compared the heavy-ion induced upset cross-section in 28, 40, and 65 nm dual-well and triple-well SRAMs over a wide range of particle LETs.
Proceedings ArticleDOI

Impact of technology scaling on the combinational logic soft error rate

TL;DR: Experimental results from alpha particle irradiation of 40-nm, 28-nm and 20-nm bulk technology circuits operating in the GHz range suggest that the combinational logic soft error rate (SER) per logic gate decreases with scaling, but the rate of decrease for the logic SER with scaling is not as high as that of the latch SER.