J
J. Maiz
Researcher at Intel
Publications - 6
Citations - 261
J. Maiz is an academic researcher from Intel. The author has contributed to research in topics: NMOS logic & SILC. The author has an hindex of 4, co-authored 6 publications receiving 255 citations.
Papers
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Proceedings ArticleDOI
BTI reliability of 45 nm high-K + metal-gate process technology
S. Pae,M. Agostinelli,M. Brazier,R. Chau,G. Dewey,Tahir Ghani,Michael L. Hattendorf,J. Hicks,Jack Portland Kavalieros,K. Kuhn,Markus Kuhn,J. Maiz,Matthew V. Metz,Kaizad Mistry,Chetan Prasad,S. Ramey,A. Roskowski,J. Sandford,C. Thomas,J. Thomas,Christopher J. Wiegand,J. Wiedemer +21 more
TL;DR: In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed.
Proceedings ArticleDOI
A high performance 180 nm generation logic technology
Simon Yang,S. Ahmed,B. Arcot,R. Arghavani,P. Bai,S. Chambers,P. Charvat,Raymond E. Cotner,R. Gasser,Tahir Ghani,Makarem A. Hussein,Chia-Hong Jan,C. Kardas,J. Maiz,P. McGregor,B. McIntyre,P. Nguyen,Paul A. Packan,Ian R. Post,Swaminathan Sivakumar,Joseph M. Steigerwald,M. Taylor,B. Tufts,S. Tyagi,M. Bohr +24 more
TL;DR: In this article, a 180 nm generation logic technology has been developed with high performance 140 nm L/sub GATE/ transistors, six layers of aluminum interconnects and low/spl epsi/ SiOF dielectrics.
Proceedings ArticleDOI
Dielectric breakdown in a 45 nm high-k/metal gate process technology
Chetan Prasad,M. Agostinelli,C. Auth,M. Brazier,R. Chau,G. Dewey,Tahir Ghani,Michael L. Hattendorf,J. Hicks,J. Jopling,Jack Portland Kavalieros,Roza Kotlyar,Markus Kuhn,K. Kuhn,J. Maiz,B. McIntyre,Matthew V. Metz,Kaizad Mistry,S. Pae,W. Rachmady,S. Ramey,A. Roskowski,J. Sandford,C. Thomas,Christopher J. Wiegand,J. Wiedemer +25 more
TL;DR: In this article, the authors present extensive breakdown results on 45nm HK+MG technology and identify the gate and substrate injection effects that contribute to the degradation of the SiON-based SiON.
Proceedings ArticleDOI
Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology
S. Pae,T. Ghani,M. Hattendorf,J. Hicks,J. Jopling,J. Maiz,K. Mistry,J. O'Donnell,Chetan Prasad,J. Wiedemer,J. Xu +10 more
TL;DR: In this paper, the authors demonstrate that SILC has no impact on products made of 45nm high-K and metal-gate transistors in an optimized high-k and high-MG process.
Proceedings ArticleDOI
Future device scaling - Beyond traditional CMOS
S. Tyagi,C. Auth,I. Ban,P. Chang,R. Chau,Tahir Ghani,C.-H. Jan,Jack Portland Kavalieros,K. Kuhn,J. Maiz,Kaizad Mistry,Ian R. Post +11 more
TL;DR: Recent advances in CMOS scaling, processing and material properties, device structure and reliability are summarized to enable technology scaling as per Moore's law.