A planar substrate device (100) integrated with fin field effect transistors (FinFETs) and a method of manufâcture comprises a silicon-on-insulator (SOI) wafer (101) comprising a substrate (103); a buried insulator layer (105) over the substrate (103); and a semiconductor layer (115) over the buried insulator layer (105). The structure (100) further comprises a FinFET (130) over the buried insulator layer (105) and a field effect transistor (FET) (131) integrated in the substrate (103), wherein the FET (127) gate is planar to the FinFET gate (125). The structure (100) further comprises retrograde well regions (104, 106, 108, 110) configured in the substrate (103). In one embodiment, the structure (100) further comprises a shallow trench isolation region (111) configured in the substrate (103).

Planar substrate devices integrated with finfets and method of manufacture

Technology-aware design of SRAM memory circuits

Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve control and reduce short channel effects. Among the likely candidates, FinFETs are the most attractive option because of their good scalability and possibilities for further SRAM performance and yield enhancement through independent gating. The enhancements to read/write margins and yield are investigated in detail for two cell designs employing independently gated FinFETs. It is shown that FinFET-based 6-T SRAM cells designed with pass-gate feedback (PGFB) achieve significant improvements in the cell read stability without area penalty. The write-ability of the cell can be improved through the use of pull-up write gating (PUWG) with a separate write word line (WWL). The benefits of these two approaches are complementary and additive, allowing for simultaneous read and write yield enhancements when the PGFB and PUWG designs are used in combination.

SRAM Read/Write Margin Enhancements Using FinFETs

In this brief, shallow-trench-isolation (STI) stress buffer techniques, including sidewall stress buffer and channel surface buffer layers, are developed to reduce the impact of compressive STI stress on the mobility of advanced n-type MOS (NMOS) devices. Our investigation shows that a 7% driving current gain at an NMOS device has been achieved, whereas no degradation at a p-type MOS (PMOS) device was observed. The same junction leakage at both the NMOS and PMOS devices was maintained. A stress relaxation model with simulation is thus proposed to account for the enhanced transport characteristics.

https://ir.nctu.edu.tw:443/bitstream/11536/9488/1/000254225500021.pdf

Strained CMOS Devices With Shallow-Trench-Isolation Stress Buffer Layers

Extremely thin SOI (ETSOI) MOSFET is an attractive candidate for 22nm technology and beyond due to its excellent short channel control, low leakage current, and immunity to random dopant fluctuation [1–5]. Short channel effects are mainly controlled by channel thickness, so there is no need for aggressive scaling of the gate dielectric. Thus the gate leakage is reduced beyond what is achievable in high-k bulk technologies. Low-power operation is further enhanced by negligible GIDL current due to the undoped channel. In addition, ETSOI devices have inherently no junction leakage by the virtue of thin silicon channel. Higher gate voltage overdrive is achieved for a given supply voltage compared to bulk technologies due to smaller subthreshold slope. This enables low-V DD logic operation. Moreover, low-V DD SRAM functionality is supported by small V T - mismatch in undoped channel [5]. In conventional CMOS technologies, complete device redesign is needed if V T changes are required. In ETSOI, however, threshold voltage is tuned through gate workfunction modulation without change in the channel doping. Thus V T tuning is to a large extent decoupled from device scaling.

Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond

A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current

Jhi-cheng Lu

Papers

A 65nm node strained SOI technology with slim spacer