Journal ArticleDOI
Investigation of Gate Sidewall Spacer Optimization From OFF-State Leakage Current Perspective in 3-nm Node Device
TLDR
In this article, the structural and material optimization of gate sidewall spacer in the perspective of off-state leakage current was performed in a 3-nm node nanoplate FET.Abstract:
In this paper, the structural and material optimization of gate sidewall spacer in the perspective of OFF-state leakage current was performed in a 3-nm node nanoplate FET (NPFET). Gate-induced drain leakage (GIDL) current, a dominant factor of OFF-state leakage current, and active performance (ON-current, ON/OFF current ratio, and dynamic performance) were co-optimized according to the structural correlation of gate sidewall spacer with other structural components such as gate, source, and drain length. By optimizing the structure for gate and spacer, intrinsic delay was improved by 9.8%, GIDL current was reduced by ~78%, and then on/off current ratio ( ${I}_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}})$ was enhanced by 4.2 times. On-current ( ${I}_{\mathrm{\scriptscriptstyle ON}}$ ) according to contact resistance ( ${R}_{\text {con}}$ ) and dynamic performance was analyzed in relation to source/drain (S/D) and spacer. Consequently, the intrinsic delay was improved by 10% and GIDL current reduced by about 92%, which enhanced ${I}_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}}$ by 7.9 times accordingly. Furthermore, by comparing structural relations between gate spacer and S/D spacer, a better structural optimization method was proposed.read more
Citations
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Journal ArticleDOI
Investigation of Electrical Characteristic Behavior Induced by Channel-Release Process in Stacked Nanosheet Gate-All-Around MOSFETs
Sihyun Kim,Munhyeon Kim,Donghyun Ryu,Kitae Lee,So Youn Kim,Junil Lee,Ryoongbin Lee,Sangwan Kim,Jong-Ho Lee,Byung-Gook Park +9 more
TL;DR: In this article, several issues attributed to the channel-release process in vertically stacked-gate-all-around MOSFETs (GAAFETs) having various nanosheet (NS) widths were rigorously investigated.
Journal ArticleDOI
Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications
Journal ArticleDOI
Design and Optimization of Triple-k Spacer Structure in Two-Stack Nanosheet FET From OFF-State Leakage Perspective
TL;DR: In this article, a triple-k spacer structure with three spacer regions consisting of two inner spacers (inner spacer 1 and inner spacer 2) formed by two atomic layer deposition (ALD) processes leveraging the inner Spacer formation-process method and outer spacer process of stack gate-all-around (GAA) process is proposed.
Journal ArticleDOI
Analysis of Self Heating Effect in DC/AC Mode in Multi-Channel GAA-Field Effect Transistor
TL;DR: In this article, the self-heating effect (SHE) of both dc and ac for a three-channel nanowire-field effect transistor (FET) is investigated and analyzed.
Journal ArticleDOI
Investigation of Sidewall High- k Interfacial Layer Effect in Gate-All-Around Structure
TL;DR: The optimized electrical characteristics were obtained and improved electrical performances were obtained in a 5-nm node nanosheet field-effect transistor (NSFET) with highly saturated ON-/OFF-current ratio.
References
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Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
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TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
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Moore's law: past, present and future
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Small-Diameter Silicon Nanowire Surfaces
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Journal ArticleDOI
Short-channel effect in fully depleted SOI MOSFETs
TL;DR: In this article, the short channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation, and it is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions.
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