K
Keshab K. Parhi
Researcher at University of Minnesota
Publications - 768
Citations - 21763
Keshab K. Parhi is an academic researcher from University of Minnesota. The author has contributed to research in topics: Decoding methods & Adaptive filter. The author has an hindex of 68, co-authored 749 publications receiving 20097 citations. Previous affiliations of Keshab K. Parhi include University of California, Berkeley & University of Warwick.
Papers
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Proceedings ArticleDOI
Classification of single-trial MEG during sentence processing for automated schizophrenia screening
TL;DR: A novel computer-aided system for assisting schizophrenia (SZ) diagnosis and the most discriminating PSDR features are selected from the right temporal, right parietal and right frontal regions and are related to alpha and beta frequency ranges may help in gaining knowledge about the abnormal neural oscillations associated with sentence-level language disorder in SZ.
Proceedings ArticleDOI
Synthesis of folded multi-dimensional DSP systems
TL;DR: A novel multi-dimensional folding transformation technique is formalized which can be used to synthesize control circuits for pipelined architectures which implement a specific class of MD DSP algorithms.
Journal ArticleDOI
Impulse Noise Correction in OFDM Systems
TL;DR: Simulation results show that the proposed novel scheme can effectively correct impulse errors that corrupt up to 20.7 % and 13.9 % of the received time-domain signal at known locations for quadrature amplitude modulation (QAM)-4 and QAM-8 modulation.
Proceedings ArticleDOI
Constrained Tensor Decomposition Optimization With Applications To Fmri Data Analysis
Bhaskar Sen,Keshab K. Parhi +1 more
TL;DR: Constrained tensor decomposition methods for model-free estimation of signals from task fMRI data are explored and an optimization model for solving the signal estimation problem from taskfMRI data is proposed.
Proceedings ArticleDOI
Low-energy programmable finite field data path architectures
TL;DR: It is concluded that the one-level pipelined fully-parallel multiplier without control circuitry consumes the least energy at component level when only one multiplication is considered, and the proposed approach is able to achieve 70% energy reduction at the expense of increasing the total instruction count by one.