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Keshab K. Parhi

Researcher at University of Minnesota

Publications -  768
Citations -  21763

Keshab K. Parhi is an academic researcher from University of Minnesota. The author has contributed to research in topics: Decoding methods & Adaptive filter. The author has an hindex of 68, co-authored 749 publications receiving 20097 citations. Previous affiliations of Keshab K. Parhi include University of California, Berkeley & University of Warwick.

Papers
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Journal ArticleDOI

Small area parallel Chien search architectures for long BCH codes

TL;DR: This paper presents a novel group matching scheme to reduce the Chien search hardware complexity by 60% for BCH(2047, 1926, 23) code as opposed to only 26% if directly applying the iterative matching algorithm.
Journal ArticleDOI

Low-Latency Successive-Cancellation List Decoders for Polar Codes With Multibit Decision

TL;DR: A multibit-decision approach that can significantly reduce latency of SCL decoders and a general decoding scheme that can perform intermediate decoding of any 2K bits simultaneously, which can reduce the overall decoding latency to as short as n/2K-2-2 cycles.
Journal ArticleDOI

RETOUCH: The Retinal OCT Fluid Detection and Segmentation Benchmark and Challenge

TL;DR: A challenge RETOUCH, which featured for the first time: all three retinal fluid types, with annotated images provided by two clinical centers, revealed that in the detection task, the performance on the automated fluid detection was within the inter-grader variability, however, in the segmentation task, fusing the automated methods produced segmentations that were superior to all individual methods, indicating the need for further improvements in the segmentsation performance.
Journal ArticleDOI

A Pipelined FFT Architecture for Real-Valued Signals

TL;DR: The proposed architecture takes advantage of the reduced number of operations of the RFFT with respect to the complex fast Fourier transform (CFFT), and requires less area while achieving higher throughput and lower latency.
BookDOI

Digit-Serial Computation

TL;DR: This document describes the development of Digit-Serial Architecture, a system for modeling and modeling the behaviour of discrete-time circuits, and some of the techniques used in that process.