K
Keshab K. Parhi
Researcher at University of Minnesota
Publications - 768
Citations - 21763
Keshab K. Parhi is an academic researcher from University of Minnesota. The author has contributed to research in topics: Decoding methods & Adaptive filter. The author has an hindex of 68, co-authored 749 publications receiving 20097 citations. Previous affiliations of Keshab K. Parhi include University of California, Berkeley & University of Warwick.
Papers
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Proceedings ArticleDOI
Reduced-latency SC polar decoder architectures
TL;DR: A novel input generating circuit (ICG) block is presented that can generate additional input signals for merged PEs on-the-fly and shows advantages of 50% decoding latency and twice throughput over the conventional one with similar hardware cost.
Journal ArticleDOI
High-level DSP synthesis using concurrent transformations, scheduling, and allocation
Ching-Yi Wang,Keshab K. Parhi +1 more
TL;DR: This paper addresses high-level synthesis methodologies for dedicated digital signal processing (DSP) architectures used in the iterative Loop-based Minnesota Architecture Synthesis (MARS) design system with a novel concurrent scheduling and resource allocation algorithm which exploits inter-iteration and intra-iterations precedence constraints.
Journal ArticleDOI
Fully Automated Segmentation of Fluid/Cyst Regions in Optical Coherence Tomography Images With Diabetic Macular Edema Using Neutrosophic Sets and Graph Algorithms
Abdolreza Rashno,Dara D. Koozekanani,Paul Drayna,Behzad Nazari,Saeed Sadri,Hossein Rabbani,Keshab K. Parhi +6 more
TL;DR: A fully automated algorithm to segment fluid-associated (fluid-filled) and cyst regions in optical coherence tomography (OCT) retina images of subjects with diabetic macular edema is presented and includes a novel approach in estimating the number of clusters in an automated manner.
Posted Content
Reduced-Latency SC Polar Decoder Architectures
TL;DR: In this paper, a parallel SC polar decoder is proposed to reduce the decoding latency by 50% with pipelining and parallel processing schemes, and a sub-structure sharing approach is employed to design the merged processing element (PE).
Journal ArticleDOI
Joint (3,k)-regular LDPC code and decoder/encoder design
Tong Zhang,Keshab K. Parhi +1 more
TL;DR: This paper presents a joint (3,k)-regular LDPC code and decoder/encoder design technique to construct a class of LDPC codes that not only have very good error-correcting capability but also exactly fit to high-speed partly parallel decoder and low-complexity encoder implementations.