M
Michael K. Harper
Researcher at Intel
Publications - 13
Citations - 714
Michael K. Harper is an academic researcher from Intel. The author has contributed to research in topics: Transistor & Layer (electronics). The author has an hindex of 7, co-authored 13 publications receiving 679 citations.
Papers
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Proceedings ArticleDOI
45nm High-k + metal gate strain-enhanced transistors
C. Auth,Annalisa Cappellani,J.-S. Chun,A. Dalis,Alison Davis,Tahir Ghani,G. Glass,Timothy E. Glassman,Michael K. Harper,Michael L. Hattendorf,P. Hentges,S. Jaloviar,Subhash M. Joshi,Jason Klaus,K. Kuhn,D. Lavric,M. Lu,H. Mariappan,Kaizad Mistry,B. Norris,Nadia M. Rahhal-Orabi,Pushkar Ranade,J. Sandford,Lucian Shifren,V. Souw,K. Tone,F. Tambwe,A. Thompson,D. Towner,T. Troeger,P. Vandervoorn,Charles H. Wallace,J. Wiedemer,Christopher J. Wiegand +33 more
TL;DR: In this article, two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper.
Patent
Feature size reduction
Elliot N. Tan,Michael K. Harper +1 more
TL;DR: In this paper, a pattern comprised of at least two first features on the substrate surface, depositing a first conformal layer on the first features and depositing the second conformal layers on the second features.
Patent
Recessed workfunction metal in CMOS transistor gates
TL;DR: In this article, a transistor gate is formed by conformally depositing the high-k dielectric into a trench between the spacers on the substrate, and then depositing a workfunction metal atop the high k Dielectric, and finally etching a portion of the sacrificial mask to expose the exposed portion.
Proceedings ArticleDOI
100 nm gate length high performance/low power CMOS transistor structure
Tahir Ghani,S. Ahmed,P. Aminzadeh,J. Bielefeld,P. Charvat,C. Chu,Michael K. Harper,P. Jacob,Chia-Hong Jan,Jack Portland Kavalieros,C. Kenyon,Ramune Nagisetty,Paul A. Packan,J. Sebastian,M. Taylor,J. Tsai,S. Tyagi,Simon Yang,M. Bohr +18 more
TL;DR: In this paper, the authors report a very high performance 100 nm gate length CMOS transistor structure operating at 1.2-1.5 V and 3 nA/m I/sub OFF.
Patent
Substrate fins with different heights
TL;DR: In this article, a device includes a number of fins, and some of the fins have greater heights than other fins, which allows the selection of different drive currents and/or transistor areas.