Rashmi Jha

TL;DR: In this article, a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2 was demonstrated.

TL;DR: In this article, the work function of metal electrodes on high/spl kappa/ dielectrics with various charge distributions was derived and a mathematical analysis including sources of errors was used to study the effect of charge distribution in gate dielectric stacks on the flatband voltage.

TL;DR: The electrical characteristics of two-terminal synaptic memory devices capable of demonstrating an analog change in conductance in response to the varying amplitude and pulse-width of the applied signal are discussed.

TL;DR: In this paper, the authors present a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity types region; forming a gate stack including a gate dielectric atop the substrate and a first metal gate conductor overlying the high-k gate dieslectric; and applying a nitrogen-based plasma to the substrate.

TL;DR: In this article, the authors report the switching characteristics of RRAM devices consisting of Ru/HfO2/TiO2-x/Ru stacks with and without an external access device.